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[82.26.13.58]) by smtp.gmail.com with ESMTPSA id p6-20020a1c7406000000b003f4272c2d10sm5083982wmc.1.2023.05.18.04.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 04:39:24 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, Rajnesh Kanwal Subject: [PATCH 0/6] Add RISC-V Virtual IRQs and IRQ filtering support Date: Thu, 18 May 2023 12:38:32 +0100 Message-Id: <20230518113838.130084-1-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 18 May 2023 09:33:46 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series adds M and HS-mode virtual interrupt and IRQ filtering support. This allows inserting virtual interrupts from M/HS-mode into S/VS-mode using mvien/hvien and mvip/hvip csrs. IRQ filtering is a use case of this change, i-e M-mode can stop delegating an interrupt to S-mode and instead enable it in MIE and receive those interrupts in M-mode and then selectively inject the interrupt using mvien and mvip. Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows M/HS-mode to assert virtual interrupts to S/VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "5.3 Interrupt filtering and virtual interrupts for supervisor level" and "6.3.2 Virtual interrupts for VS level". Most of the testing is done by hacking around OpenSBI and linux host. The changes for those can be found at [2] and [3]. It's my first touch on RISC-V qemu IRQ subsystem. Any feedback would be much appreciated. The change can also be found on github [1]. TODO: This change doesn't support delegating virtual interrupts injected by M-mode to VS-mode by the Hypervisor. This is true for bits 13:63 only. Thanks Rajnesh [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf [1]: https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/riscv_irq_filter [2]: https://github.com/rajnesh-kanwal/opensbi/tree/dev/rkanwal/irq_filter [3]: https://github.com/rajnesh-kanwal/linux/commits/dev/rkanwal/aia_irq_filter Rajnesh Kanwal (6): target/riscv: Without H-mode mask all HS mode inturrupts in mie. target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled target/riscv: Split interrupt logic from riscv_cpu_update_mip. target/riscv: Add M-mode virtual interrupt and IRQ filtering support. target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. target/riscv/cpu.c | 9 +- target/riscv/cpu.h | 23 ++ target/riscv/cpu_bits.h | 6 + target/riscv/cpu_helper.c | 87 +++++-- target/riscv/csr.c | 477 ++++++++++++++++++++++++++++++++++---- target/riscv/machine.c | 6 + 6 files changed, 541 insertions(+), 67 deletions(-) -- 2.25.1