[PATCH v2 0/6] target/riscv: Add support for BF16 extensions

From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, dbarboza@ventanamicro.com,
	zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
	lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v2 0/6] target/riscv: Add support for BF16 extensions
Date: Thu, 15 Jun 2023 14:32:56 +0800	[thread overview]
Message-ID: <20230615063302.102409-1-liweiwei@iscas.ac.cn> (raw)

Specification for BF16 extensions can be found in:
https://github.com/riscv/riscv-bfloat16

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-bf16-upstream-v2

v2:
* Update dependancy check for BF16 extensions in patch 1 and patch 4
* Update encodings for BF16 instructions in patch 2,3,4
* Add disas support for BF16 instructions in patch 6

Weiwei Li (6):
  target/riscv: Add properties for BF16 extensions
  target/riscv: Add support for Zfbfmin extension
  target/riscv: Add support for Zvfbfmin extension
  target/riscv: Add support for Zvfbfwma extension
  target/riscv: Expose properties for BF16 extensions
  target/riscv: Add disas support for BF16 extensions

 disas/riscv.c                              |  44 ++++++
 target/riscv/cpu.c                         |  27 ++++
 target/riscv/cpu_cfg.h                     |   3 +
 target/riscv/fpu_helper.c                  |  12 ++
 target/riscv/helper.h                      |  10 ++
 target/riscv/insn32.decode                 |  12 ++
 target/riscv/insn_trans/trans_rvbf16.c.inc | 175 +++++++++++++++++++++
 target/riscv/insn_trans/trans_rvzfh.c.inc  |  12 +-
 target/riscv/translate.c                   |   1 +
 target/riscv/vector_helper.c               |  17 ++
 10 files changed, 307 insertions(+), 6 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc

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2.25.1