From: Jason Chien <jason.chien@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Jason Chien <jason.chien@sifive.com>
Subject: [PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS
Date: Tue, 11 Jul 2023 07:03:56 +0000 [thread overview]
Message-ID: <20230711070402.5846-1-jason.chien@sifive.com> (raw)
In v2, I rebased the patch on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
However, I forgot to add "Reviewed-by" in v2, so I add them in v3.
Jason Chien (1):
target/riscv: Add Zihintntl extension ISA string to DTS
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
--
2.17.1
next reply other threads:[~2023-07-11 7:04 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-11 7:03 Jason Chien [this message]
2023-07-11 7:03 ` [PATCH v3 1/1] target/riscv: Add Zihintntl extension ISA string to DTS Jason Chien
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