From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 00/65] riscv-to-apply queue
Date: Fri, 8 Sep 2023 16:03:26 +1000 [thread overview]
Message-ID: <20230908060431.1903919-1-alistair.francis@wdc.com> (raw)
The following changes since commit 03a3a62fbd0aa5227e978eef3c67d3978aec9e5f:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-09-07 10:29:06 -0400)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230908
for you to fetch changes up to 69749970db9f1b05c8cd77a7bbb45e4e156f7d33:
target/riscv/cpu.c: consider user option with RVG (2023-09-08 15:57:39 +1000)
----------------------------------------------------------------
First RISC-V PR for 8.2
* Remove 'host' CPU from TCG
* riscv_htif Fixup printing on big endian hosts
* Add zmmul isa string
* Add smepmp isa string
* Fix page_check_range use in fault-only-first
* Use existing lookup tables for MixColumns
* Add RISC-V vector cryptographic instruction set support
* Implement WARL behaviour for mcountinhibit/mcounteren
* Add Zihintntl extension ISA string to DTS
* Fix zfa fleq.d and fltq.d
* Fix upper/lower mtime write calculation
* Make rtc variable names consistent
* Use abi type for linux-user target_ucontext
* Add RISC-V KVM AIA Support
* Fix riscv,pmu DT node path in the virt machine
* Update CSR bits name for svadu extension
* Mark zicond non-experimental
* Fix satp_mode_finalize() when satp_mode.supported = 0
* Fix non-KVM --enable-debug build
* Add new extensions to hwprobe
* Use accelerated helper for AES64KS1I
* Allocate itrigger timers only once
* Respect mseccfg.RLB for pmpaddrX changes
* Align the AIA model to v1.0 ratified spec
* Don't read the CSR in riscv_csrrw_do64
* Add the 'max' CPU, detect user choice in TCG
----------------------------------------------------------------
Akihiko Odaki (1):
target/riscv: Allocate itrigger timers only once
Ard Biesheuvel (2):
target/riscv: Use existing lookup tables for MixColumns
target/riscv: Use accelerated helper for AES64KS1I
Conor Dooley (1):
hw/riscv: virt: Fix riscv,pmu DT node path
Daniel Henrique Barboza (26):
target/riscv/cpu.c: do not run 'host' CPU with TCG
target/riscv/cpu.c: add zmmul isa string
target/riscv/cpu.c: add smepmp isa string
target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
hw/riscv/virt.c: fix non-KVM --enable-debug build
hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
target/riscv/cpu.c: skip 'bool' check when filtering KVM props
target/riscv/cpu.c: split kvm prop handling to its own helper
target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
target/riscv/cpu.c: limit cfg->vext_spec log message
target/riscv: add 'max' CPU type
avocado, risc-v: add tuxboot tests for 'max' CPU
target/riscv: deprecate the 'any' CPU type
target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
target/riscv: make CPUCFG() macro public
target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
target/riscv/cpu.c: consider user option with RVG
Dickon Hood (2):
target/riscv: Refactor translation of vector-widening instruction
target/riscv: Add Zvbb ISA extension support
Jason Chien (3):
target/riscv: Add Zihintntl extension ISA string to DTS
hw/intc: Fix upper/lower mtime write calculation
hw/intc: Make rtc variable names consistent
Kiran Ostrolenk (4):
target/riscv: Refactor some of the generic vector functionality
target/riscv: Refactor vector-vector translation macro
target/riscv: Refactor some of the generic vector functionality
target/riscv: Add Zvknh ISA extension support
LIU Zhiwei (3):
target/riscv: Fix page_check_range use in fault-only-first
target/riscv: Fix zfa fleq.d and fltq.d
linux-user/riscv: Use abi type for target_ucontext
Lawrence Hunter (2):
target/riscv: Add Zvbc ISA extension support
target/riscv: Add Zvksh ISA extension support
Leon Schuermann (1):
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
Max Chou (3):
crypto: Create sm4_subword
crypto: Add SM4 constant parameter CK
target/riscv: Add Zvksed ISA extension support
Nazar Kazakov (4):
target/riscv: Remove redundant "cpu_vl == 0" checks
target/riscv: Move vector translation checks
target/riscv: Add Zvkned ISA extension support
target/riscv: Add Zvkg ISA extension support
Nikita Shubin (1):
target/riscv: don't read CSR in riscv_csrrw_do64
Rob Bradford (1):
target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
Robbin Ehn (1):
linux-user/riscv: Add new extensions to hwprobe
Thomas Huth (2):
hw/char/riscv_htif: Fix printing of console characters on big endian hosts
hw/char/riscv_htif: Fix the console syscall on big endian hosts
Tommy Wu (1):
target/riscv: Align the AIA model to v1.0 ratified spec
Vineet Gupta (1):
riscv: zicond: make non-experimental
Weiwei Li (1):
target/riscv: Update CSR bits name for svadu extension
Yong-Xuan Wang (5):
target/riscv: support the AIA device emulation with KVM enabled
target/riscv: check the in-kernel irqchip support
target/riscv: Create an KVM AIA irqchip
target/riscv: update APLIC and IMSIC to support KVM AIA
target/riscv: select KVM AIA in riscv virt machine
docs/about/deprecated.rst | 12 +
include/crypto/aes.h | 7 +
include/crypto/sm4.h | 9 +
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.h | 2 +
target/riscv/cpu_bits.h | 8 +-
target/riscv/cpu_cfg.h | 9 +
target/riscv/debug.h | 3 +-
target/riscv/helper.h | 98 +++
target/riscv/kvm_riscv.h | 5 +
target/riscv/vector_internals.h | 228 +++++++
target/riscv/insn32.decode | 58 ++
crypto/aes.c | 4 +-
crypto/sm4.c | 10 +
hw/char/riscv_htif.c | 12 +-
hw/intc/riscv_aclint.c | 11 +-
hw/intc/riscv_aplic.c | 52 +-
hw/intc/riscv_imsic.c | 25 +-
hw/riscv/virt.c | 374 ++++++------
linux-user/riscv/signal.c | 4 +-
linux-user/syscall.c | 14 +-
target/arm/tcg/crypto_helper.c | 10 +-
target/riscv/cpu.c | 625 ++++++++++++++-----
target/riscv/cpu_helper.c | 6 +-
target/riscv/crypto_helper.c | 51 +-
target/riscv/csr.c | 54 +-
target/riscv/debug.c | 15 +-
target/riscv/kvm.c | 209 ++++++-
target/riscv/pmp.c | 4 +
target/riscv/translate.c | 1 +
target/riscv/vcrypto_helper.c | 970 ++++++++++++++++++++++++++++++
target/riscv/vector_helper.c | 245 +-------
target/riscv/vector_internals.c | 81 +++
target/riscv/insn_trans/trans_rvv.c.inc | 171 +++---
target/riscv/insn_trans/trans_rvvk.c.inc | 606 +++++++++++++++++++
target/riscv/insn_trans/trans_rvzfa.c.inc | 4 +-
target/riscv/meson.build | 4 +-
tests/avocado/tuxrun_baselines.py | 32 +
38 files changed, 3224 insertions(+), 810 deletions(-)
create mode 100644 target/riscv/vector_internals.h
create mode 100644 target/riscv/vcrypto_helper.c
create mode 100644 target/riscv/vector_internals.c
create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc
next reply other threads:[~2023-09-08 6:05 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 6:03 Alistair Francis [this message]
2023-09-08 6:03 ` [PULL 01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG Alistair Francis
2023-09-08 6:03 ` [PULL 02/65] hw/char/riscv_htif: Fix printing of console characters on big endian hosts Alistair Francis
2023-09-08 6:03 ` [PULL 03/65] hw/char/riscv_htif: Fix the console syscall " Alistair Francis
2023-09-08 6:15 ` Michael Tokarev
2023-09-08 6:03 ` [PULL 04/65] target/riscv/cpu.c: add zmmul isa string Alistair Francis
2023-09-08 6:03 ` [PULL 05/65] target/riscv/cpu.c: add smepmp " Alistair Francis
2023-09-08 6:03 ` [PULL 06/65] target/riscv: Fix page_check_range use in fault-only-first Alistair Francis
2023-09-08 6:03 ` [PULL 07/65] target/riscv: Use existing lookup tables for MixColumns Alistair Francis
2023-09-08 6:03 ` [PULL 08/65] target/riscv: Refactor some of the generic vector functionality Alistair Francis
2023-09-08 6:03 ` [PULL 09/65] target/riscv: Refactor vector-vector translation macro Alistair Francis
2023-09-08 6:03 ` [PULL 10/65] target/riscv: Remove redundant "cpu_vl == 0" checks Alistair Francis
2023-09-08 6:03 ` [PULL 11/65] target/riscv: Add Zvbc ISA extension support Alistair Francis
2023-09-08 6:03 ` [PULL 12/65] target/riscv: Move vector translation checks Alistair Francis
2023-09-08 6:03 ` [PULL 13/65] target/riscv: Refactor translation of vector-widening instruction Alistair Francis
2023-09-08 6:03 ` [PULL 14/65] target/riscv: Refactor some of the generic vector functionality Alistair Francis
2023-09-08 6:03 ` [PULL 15/65] target/riscv: Add Zvbb ISA extension support Alistair Francis
2023-09-08 6:03 ` [PULL 16/65] target/riscv: Add Zvkned " Alistair Francis
2023-09-08 6:03 ` [PULL 17/65] target/riscv: Add Zvknh " Alistair Francis
2023-09-08 6:03 ` [PULL 18/65] target/riscv: Add Zvksh " Alistair Francis
2023-09-08 6:03 ` [PULL 19/65] target/riscv: Add Zvkg " Alistair Francis
2023-09-08 6:03 ` [PULL 20/65] crypto: Create sm4_subword Alistair Francis
2023-09-08 6:03 ` [PULL 21/65] crypto: Add SM4 constant parameter CK Alistair Francis
2023-09-08 6:03 ` [PULL 22/65] target/riscv: Add Zvksed ISA extension support Alistair Francis
2023-09-08 6:03 ` [PULL 23/65] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren Alistair Francis
2023-09-08 6:03 ` [PULL 24/65] target/riscv: Add Zihintntl extension ISA string to DTS Alistair Francis
2023-09-08 6:03 ` [PULL 25/65] target/riscv: Fix zfa fleq.d and fltq.d Alistair Francis
2023-09-08 6:03 ` [PULL 26/65] hw/intc: Fix upper/lower mtime write calculation Alistair Francis
2023-09-08 6:03 ` [PULL 27/65] hw/intc: Make rtc variable names consistent Alistair Francis
2023-09-08 6:03 ` [PULL 28/65] linux-user/riscv: Use abi type for target_ucontext Alistair Francis
2023-09-08 6:03 ` [PULL 29/65] target/riscv: support the AIA device emulation with KVM enabled Alistair Francis
2023-09-08 6:03 ` [PULL 30/65] target/riscv: check the in-kernel irqchip support Alistair Francis
2023-09-08 6:03 ` [PULL 31/65] target/riscv: Create an KVM AIA irqchip Alistair Francis
2023-09-08 6:03 ` [PULL 32/65] target/riscv: update APLIC and IMSIC to support KVM AIA Alistair Francis
2023-09-08 6:03 ` [PULL 33/65] target/riscv: select KVM AIA in riscv virt machine Alistair Francis
2023-09-08 6:04 ` [PULL 34/65] hw/riscv: virt: Fix riscv,pmu DT node path Alistair Francis
2023-09-08 6:04 ` [PULL 35/65] target/riscv: Update CSR bits name for svadu extension Alistair Francis
2023-09-08 6:04 ` [PULL 36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 Alistair Francis
2023-09-08 6:04 ` [PULL 37/65] riscv: zicond: make non-experimental Alistair Francis
2023-09-08 6:04 ` [PULL 38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build Alistair Francis
2023-09-08 6:04 ` [PULL 39/65] hw/intc/riscv_aplic.c " Alistair Francis
2023-09-08 6:04 ` [PULL 40/65] linux-user/riscv: Add new extensions to hwprobe Alistair Francis
2023-09-08 6:04 ` [PULL 41/65] target/riscv: Use accelerated helper for AES64KS1I Alistair Francis
2023-09-08 6:04 ` [PULL 42/65] target/riscv: Allocate itrigger timers only once Alistair Francis
2023-09-08 6:04 ` [PULL 43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes Alistair Francis
2023-09-08 6:04 ` [PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec Alistair Francis
2023-09-08 6:04 ` [PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64 Alistair Francis
2023-09-08 6:04 ` [PULL 46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Alistair Francis
2023-09-08 6:04 ` [PULL 47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props Alistair Francis
2023-09-08 6:04 ` [PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper Alistair Francis
2023-09-08 13:21 ` Philippe Mathieu-Daudé
2023-09-10 8:58 ` Daniel Henrique Barboza
2023-09-11 2:15 ` Alistair Francis
2023-09-08 6:04 ` [PULL 49/65] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] Alistair Francis
2023-09-08 6:04 ` [PULL 50/65] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] Alistair Francis
2023-09-08 6:04 ` [PULL 51/65] target/riscv/cpu.c: split vendor " Alistair Francis
2023-09-08 6:04 ` [PULL 52/65] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array() Alistair Francis
2023-09-08 6:04 ` [PULL 53/65] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() Alistair Francis
2023-09-08 6:04 ` [PULL 54/65] target/riscv/cpu.c: limit cfg->vext_spec log message Alistair Francis
2023-09-08 6:04 ` [PULL 55/65] target/riscv: add 'max' CPU type Alistair Francis
2023-09-08 6:04 ` [PULL 56/65] avocado, risc-v: add tuxboot tests for 'max' CPU Alistair Francis
2023-09-08 6:04 ` [PULL 57/65] target/riscv: deprecate the 'any' CPU type Alistair Francis
2023-09-08 6:04 ` [PULL 58/65] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Alistair Francis
2023-09-08 6:04 ` [PULL 59/65] target/riscv: make CPUCFG() macro public Alistair Francis
2023-09-08 6:04 ` [PULL 60/65] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Alistair Francis
2023-09-08 6:04 ` [PULL 61/65] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Alistair Francis
2023-09-08 6:04 ` [PULL 62/65] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Alistair Francis
2023-09-08 6:04 ` [PULL 63/65] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Alistair Francis
2023-09-08 6:04 ` [PULL 64/65] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Alistair Francis
2023-09-08 6:04 ` [PULL 65/65] target/riscv/cpu.c: consider user option with RVG Alistair Francis
2023-09-08 6:38 ` [PULL 00/65] riscv-to-apply queue Michael Tokarev
2023-09-11 2:37 ` Alistair Francis
2023-09-08 11:06 ` Stefan Hajnoczi
2023-09-11 13:38 ` Daniel Henrique Barboza
2023-09-11 14:07 ` Stefan Hajnoczi
2024-01-10 8:56 Alistair Francis
2024-01-10 16:21 ` Peter Maydell
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