From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v4 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
Date: Thu, 15 Feb 2024 19:39:50 -0300 [thread overview]
Message-ID: <20240215223955.969568-2-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20240215223955.969568-1-dbarboza@ventanamicro.com>
Recent changes in options handling removed the 'mmu' default the bare
CPUs had, meaning that we must enable 'mmu' by hand when using the
rva22s64 profile CPU.
Given that this profile is setting a satp mode, it already implies that
we need a 'mmu'. Enable the 'mmu' in this case.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index dd5228c288..ee4c349972 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1075,6 +1075,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
#ifndef CONFIG_USER_ONLY
if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
+ object_property_set_bool(obj, "mmu", true, NULL);
const char *satp_prop = satp_mode_str(profile->satp_mode,
riscv_cpu_is_32bit(cpu));
object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
--
2.43.0
next prev parent reply other threads:[~2024-02-15 22:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-15 22:39 [PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework Daniel Henrique Barboza
2024-02-15 22:39 ` Daniel Henrique Barboza [this message]
2024-02-15 22:39 ` [PATCH v4 2/6] target/riscv: add riscv,isa to named features Daniel Henrique Barboza
2024-02-15 22:39 ` [PATCH v4 3/6] target/riscv: add remaining " Daniel Henrique Barboza
2024-02-15 22:39 ` [PATCH v4 4/6] target/riscv: Reset henvcfg to zero Daniel Henrique Barboza
2024-02-15 22:39 ` [PATCH v4 5/6] target/riscv: Gate hardware A/D PTE bit updating Daniel Henrique Barboza
2024-02-15 22:39 ` [PATCH v4 6/6] target/riscv: Promote svade to a normal extension Daniel Henrique Barboza
2024-02-15 23:49 ` [PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework Alistair Francis
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