From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org,
qemu-s390x@nongnu.org, qemu-ppc@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Nicholas Piggin" <npiggin@gmail.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Michael Rolnik" <mrolnik@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Song Gao" <gaosong@loongson.cn>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Stafford Horne" <shorne@gmail.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Thomas Huth" <thuth@redhat.com>,
"David Hildenbrand" <david@redhat.com>,
"Ilya Leoshkevich" <iii@linux.ibm.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Artyom Tarasenko" <atar4qemu@gmail.com>,
"Max Filippov" <jcmvbkbc@gmail.com>
Subject: [PULL 11/38] target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'
Date: Fri, 26 Apr 2024 21:41:31 +0200 [thread overview]
Message-ID: <20240426194200.43723-12-philmd@linaro.org> (raw)
In-Reply-To: <20240426194200.43723-1-philmd@linaro.org>
accel/tcg/ files requires the following definitions:
- TARGET_LONG_BITS
- TARGET_PAGE_BITS
- TARGET_PHYS_ADDR_SPACE_BITS
- TCG_GUEST_DEFAULT_MO
The first 3 are defined in "cpu-param.h". The last one
in "cpu.h", with a bunch of definitions irrelevant for
TCG. By moving the TCG_GUEST_DEFAULT_MO definition to
"cpu-param.h", we can simplify various accel/tcg includes.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20231211212003.21686-4-philmd@linaro.org>
---
target/alpha/cpu-param.h | 3 +++
target/alpha/cpu.h | 3 ---
target/arm/cpu-param.h | 8 +++++---
target/arm/cpu.h | 3 ---
target/avr/cpu-param.h | 2 ++
target/avr/cpu.h | 2 --
target/hppa/cpu-param.h | 8 ++++++++
target/hppa/cpu.h | 6 ------
target/i386/cpu-param.h | 3 +++
target/i386/cpu.h | 3 ---
target/loongarch/cpu-param.h | 2 ++
target/loongarch/cpu.h | 2 --
target/microblaze/cpu-param.h | 3 +++
target/microblaze/cpu.h | 3 ---
target/mips/cpu-param.h | 2 ++
target/mips/cpu.h | 2 --
target/openrisc/cpu-param.h | 2 ++
target/openrisc/cpu.h | 2 --
target/ppc/cpu-param.h | 2 ++
target/ppc/cpu.h | 2 --
target/riscv/cpu-param.h | 2 ++
target/riscv/cpu.h | 2 --
target/s390x/cpu-param.h | 6 ++++++
target/s390x/cpu.h | 3 ---
target/sparc/cpu-param.h | 23 +++++++++++++++++++++++
target/sparc/cpu.h | 23 -----------------------
target/xtensa/cpu-param.h | 3 +++
target/xtensa/cpu.h | 3 ---
28 files changed, 66 insertions(+), 62 deletions(-)
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index c969cb016b..5ce213a9a1 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -27,4 +27,7 @@
# define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#endif
+/* Alpha processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 7188a409a0..f9e2ecb90a 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -24,9 +24,6 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
-/* Alpha processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index da3243ab21..2d5f3aa312 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -27,14 +27,16 @@
# else
# define TARGET_PAGE_BITS 12
# endif
-#else
+#else /* !CONFIG_USER_ONLY */
/*
* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
* have to support 1K tiny pages.
*/
# define TARGET_PAGE_BITS_VARY
# define TARGET_PAGE_BITS_MIN 10
-
-#endif
+#endif /* !CONFIG_USER_ONLY */
+
+/* ARM processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO (0)
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 97997dbd08..17efc5d565 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,9 +30,6 @@
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
-/* ARM processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
#ifdef TARGET_AARCH64
#define KVM_HAVE_MCE_INJECTION 1
#endif
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 9a92bc74fc..93c2f470d0 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -32,4 +32,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define TCG_GUEST_DEFAULT_MO 0
+
#endif
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d185d20dcb..4725535102 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -30,8 +30,6 @@
#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
-#define TCG_GUEST_DEFAULT_MO 0
-
/*
* AVR has two memory spaces, data & code.
* e.g. both have 0 address
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index bb3d7ef6f7..473d489f01 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -21,4 +21,12 @@
#define TARGET_PAGE_BITS 12
+/* PA-RISC 1.x processors have a strong memory model. */
+/*
+ * ??? While we do not yet implement PA-RISC 2.0, those processors have
+ * a weak memory model, but with TLB bits that force ordering on a per-page
+ * basis. It's probably easier to fall back to a strong memory model.
+ */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index a072d0bb63..fb2e4c4a98 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -25,12 +25,6 @@
#include "qemu/cpu-float.h"
#include "qemu/interval-tree.h"
-/* PA-RISC 1.x processors have a strong memory model. */
-/* ??? While we do not yet implement PA-RISC 2.0, those processors have
- a weak memory model, but with TLB bits that force ordering on a per-page
- basis. It's probably easier to fall back to a strong memory model. */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#define MMU_ABS_W_IDX 6
#define MMU_ABS_IDX 7
#define MMU_KERNEL_IDX 8
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index 911b4cd51b..5e15335203 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -24,4 +24,7 @@
#endif
#define TARGET_PAGE_BITS 12
+/* The x86 has a strong memory model with some store-after-load re-ordering */
+#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+
#endif
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6112e27bfd..565c7a98c3 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -30,9 +30,6 @@
#define XEN_NR_VIRQS 24
-/* The x86 has a strong memory model with some store-after-load re-ordering */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
#define KVM_HAVE_MCE_INJECTION 1
/* support for self modifying code even if the modified instruction is
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index cfe195db4e..db5ad1c69f 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -14,4 +14,6 @@
#define TARGET_PAGE_BITS 12
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ec37579fd6..abb01b2cc7 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -39,8 +39,6 @@
#define IOCSR_MEM_SIZE 0x428
-#define TCG_GUEST_DEFAULT_MO (0)
-
#define FCSR0_M1 0x1f /* FCSR1 mask, Enables */
#define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */
#define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index 9770b0eb52..e530fead1c 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -29,4 +29,7 @@
/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
#define TARGET_PAGE_BITS 12
+/* MicroBlaze is always in-order. */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index c0c7574dbd..3e5a3e5c60 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -24,9 +24,6 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
-/* MicroBlaze is always in-order. */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
typedef struct CPUArchState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 594c91a156..6f6ac1688f 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -30,4 +30,6 @@
#define TARGET_PAGE_BITS_MIN 12
#endif
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7329226d39..3e906a175a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -10,8 +10,6 @@
#include "hw/clock.h"
#include "mips-defs.h"
-#define TCG_GUEST_DEFAULT_MO (0)
-
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
/* MSA Context */
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 3f08207485..fbfc0f568b 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -13,4 +13,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b1b7db5cbd..c9fe9ae12d 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -24,8 +24,6 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
-#define TCG_GUEST_DEFAULT_MO (0)
-
/**
* OpenRISCCPUClass:
* @parent_realize: The parent class' realize handler.
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index b7ad52de03..77c5ed9a67 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -40,4 +40,6 @@
# define TARGET_PAGE_BITS 12
#endif
+#define TCG_GUEST_DEFAULT_MO 0
+
#endif
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 67e6b2effd..0ac55d6b25 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -29,8 +29,6 @@
#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
-#define TCG_GUEST_DEFAULT_MO 0
-
#define TARGET_PAGE_BITS_64K 16
#define TARGET_PAGE_BITS_16M 24
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index b2a9396dec..1fbd64939d 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -28,4 +28,6 @@
* - M mode HLV/HLVX/HSV 0b111
*/
+#define TCG_GUEST_DEFAULT_MO 0
+
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3b1a02b944..2d0c02c35b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -43,8 +43,6 @@ typedef struct CPUArchState CPURISCVState;
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
-#define TCG_GUEST_DEFAULT_MO 0
-
/*
* RISC-V-specific extra insn start words:
* 1: Original instruction opcode
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index 84ca08626b..11d23b600d 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -13,4 +13,10 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
+/*
+ * The z/Architecture has a strong memory model with some
+ * store-after-load re-ordering.
+ */
+#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+
#endif
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 43a46a5a06..414680eed1 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -33,9 +33,6 @@
#define ELF_MACHINE_UNAME "S390X"
-/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
#define TARGET_HAS_PRECISE_SMC
#define TARGET_INSN_START_EXTRA_WORDS 2
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index cb11980404..82293fb844 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -23,4 +23,27 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+/*
+ * From Oracle SPARC Architecture 2015:
+ *
+ * Compatibility notes: The PSO memory model described in SPARC V8 and
+ * SPARC V9 compatibility architecture specifications was never implemented
+ * in a SPARC V9 implementation and is not included in the Oracle SPARC
+ * Architecture specification.
+ *
+ * The RMO memory model described in the SPARC V9 specification was
+ * implemented in some non-Sun SPARC V9 implementations, but is not
+ * directly supported in Oracle SPARC Architecture 2015 implementations.
+ *
+ * Therefore always use TSO in QEMU.
+ *
+ * D.5 Specification of Partial Store Order (PSO)
+ * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
+ *
+ * D.6 Specification of Total Store Order (TSO)
+ * ... PSO with the additional requirement that all [stores] are followed
+ * by an implied MEMBAR #StoreStore.
+ */
+#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
+
#endif
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index f3cdd17c62..dfd9512a21 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -6,29 +6,6 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
-/*
- * From Oracle SPARC Architecture 2015:
- *
- * Compatibility notes: The PSO memory model described in SPARC V8 and
- * SPARC V9 compatibility architecture specifications was never implemented
- * in a SPARC V9 implementation and is not included in the Oracle SPARC
- * Architecture specification.
- *
- * The RMO memory model described in the SPARC V9 specification was
- * implemented in some non-Sun SPARC V9 implementations, but is not
- * directly supported in Oracle SPARC Architecture 2015 implementations.
- *
- * Therefore always use TSO in QEMU.
- *
- * D.5 Specification of Partial Store Order (PSO)
- * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
- *
- * D.6 Specification of Total Store Order (TSO)
- * ... PSO with the additional requirement that all [stores] are followed
- * by an implied MEMBAR #StoreStore.
- */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
-
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
#define TARGET_FCCREGS 1
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index b1da0555de..0000725f2f 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -17,4 +17,7 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+/* Xtensa processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 6b8d0636d2..9f2341d856 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -34,9 +34,6 @@
#include "hw/clock.h"
#include "xtensa-isa.h"
-/* Xtensa processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
enum {
/* Additional instructions */
XTENSA_OPTION_CODE_DENSITY,
--
2.41.0
next prev parent reply other threads:[~2024-04-26 19:52 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 19:41 [PULL 00/38] Exec / accelerators patches Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 01/38] exec: Rename NEED_CPU_H -> COMPILING_PER_TARGET Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 02/38] exec: Reduce tlb_set_dirty() declaration scope Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 03/38] exec: Include 'cpu.h' before validating CPUArchState placement Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 04/38] exec: Expose 'target_page.h' API to user emulation Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 05/38] accel: Include missing 'exec/cpu_ldst.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 06/38] gdbstub: Include missing 'hw/core/cpu.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 07/38] gdbstub: Simplify #ifdef'ry in helpers.h Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 08/38] gdbstub: Avoid including 'cpu.h' in 'gdbstub/helpers.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 09/38] semihosting/uaccess: Avoid including 'cpu.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 10/38] semihosting/guestfd: Remove unused 'semihosting/uaccess.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` Philippe Mathieu-Daudé [this message]
2024-04-26 19:41 ` [PULL 12/38] target/ppc/excp_helper: Avoid 'abi_ptr' in system emulation Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 13/38] target/sparc: Replace abi_ulong by uint32_t for TARGET_ABI32 Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 14/38] target/i386: Include missing 'exec/exec-all.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 15/38] accel/tcg: Un-inline retaddr helpers to 'user-retaddr.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 16/38] accel/tcg: Include missing 'hw/core/cpu.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 17/38] accel/tcg: Include missing headers in 'tb-jmp-cache.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 18/38] accel/tcg: Rename load-extract/store-insert headers using .h.inc suffix Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 19/38] accel/tcg: Rename helper-head.h -> helper-head.h.inc Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 20/38] accel/whpx: Use accel-specific per-vcpu @dirty field Philippe Mathieu-Daudé
2024-04-28 20:12 ` Volker Rümelin
2024-04-29 8:22 ` Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 21/38] accel/nvmm: " Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 22/38] accel/hvf: " Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 23/38] exec/cpu-all: Reduce 'qemu/rcu.h' header inclusion Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 24/38] exec/cpu-all: Remove unused 'qemu/thread.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 25/38] exec/cpu-all: Remove unused tswapls() definitions Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 26/38] exec: Declare target_words_bigendian() in 'exec/tswap.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 27/38] exec: Move [b]tswapl() declarations to 'exec/user/tswap-target.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 28/38] exec/user: Do not include 'cpu.h' in 'abitypes.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 29/38] exec: Declare abi_ptr type in its own 'abi_ptr.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 30/38] exec: Declare MMUAccessType type in 'mmu-access-type.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 31/38] exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 32/38] exec: Restrict TCG specific declarations of 'cputlb.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 33/38] exec: Restrict 'cpu_ldst.h' to TCG accelerator Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 34/38] exec: Rename 'exec/user/guest-base.h' as 'user/guest-base.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 35/38] exec: Restrict inclusion of 'user/guest-base.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 36/38] exec: Move CPUTLBEntry helpers to cputlb.c Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 37/38] hw/core: Avoid including the full 'hw/core/cpu.h' in 'tcg-cpu-ops.h' Philippe Mathieu-Daudé
2024-04-26 19:41 ` [PULL 38/38] plugins: Include missing 'qemu/bitmap.h' header Philippe Mathieu-Daudé
2024-04-27 14:47 ` [PULL 00/38] Exec / accelerators patches Richard Henderson
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