From: Babu Moger <babu.moger@amd.com>
To: David Edmondson <dme@dme.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
Eduardo Habkost <ehabkost@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM
Date: Thu, 1 Jul 2021 16:24:51 -0500 [thread overview]
Message-ID: <31dce00c-71bf-6d30-a1d2-f0b6ce743db2@amd.com> (raw)
In-Reply-To: <cunpmww227f.fsf@dme.org>
David, Are you still working on v2 of these series? I was going to test
and review. Thanks
> -----Original Message-----
> From: David Edmondson <dme@dme.org>
> Sent: Tuesday, June 8, 2021 3:25 AM
> To: qemu-devel@nongnu.org
> Cc: kvm@vger.kernel.org; Eduardo Habkost <ehabkost@redhat.com>; Paolo
> Bonzini <pbonzini@redhat.com>; Marcelo Tosatti <mtosatti@redhat.com>;
> Richard Henderson <richard.henderson@linaro.org>; Moger, Babu
> <Babu.Moger@amd.com>
> Subject: Re: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan
> VM
>
> On Thursday, 2021-05-20 at 15:56:40 +01, David Edmondson wrote:
>
> > AMD EPYC-Milan CPUs introduced support for protection keys, previously
> > available only with Intel CPUs.
> >
> > AMD chose to place the XSAVE state component for the protection keys
> > at a different offset in the XSAVE state area than that chosen by
> > Intel.
> >
> > To accommodate this, modify QEMU to behave appropriately on AMD
> > systems, allowing a VM to properly take advantage of the new feature.
> >
> > Further, avoid manipulating XSAVE state components that are not
> > present on AMD systems.
> >
> > The code in patch 6 that changes the CPUID 0x0d leaf is mostly dumped
> > somewhere that seemed to work - I'm not sure where it really belongs.
>
> Ping - any thoughts about this approach?
>
> > David Edmondson (7):
> > target/i386: Declare constants for XSAVE offsets
> > target/i386: Use constants for XSAVE offsets
> > target/i386: Clarify the padding requirements of X86XSaveArea
> > target/i386: Prepare for per-vendor X86XSaveArea layout
> > target/i386: Introduce AMD X86XSaveArea sub-union
> > target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd
> > target/i386: Manipulate only AMD XSAVE state on AMD
> >
> > target/i386/cpu.c | 19 +++++----
> > target/i386/cpu.h | 80 ++++++++++++++++++++++++++++--------
> > target/i386/kvm/kvm.c | 57 +++++++++----------------
> > target/i386/tcg/fpu_helper.c | 20 ++++++---
> > target/i386/xsave_helper.c | 70 +++++++++++++++++++------------
> > 5 files changed, 152 insertions(+), 94 deletions(-)
> >
> > --
> > 2.30.2
>
> dme.
> --
> You know your green from your red.
next prev parent reply other threads:[~2021-07-01 21:31 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 14:56 [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM David Edmondson
2021-05-20 14:56 ` [RFC PATCH 1/7] target/i386: Declare constants for XSAVE offsets David Edmondson
2021-05-20 14:56 ` [RFC PATCH 2/7] target/i386: Use " David Edmondson
2021-05-20 14:56 ` [RFC PATCH 3/7] target/i386: Clarify the padding requirements of X86XSaveArea David Edmondson
2021-05-20 14:56 ` [RFC PATCH 4/7] target/i386: Prepare for per-vendor X86XSaveArea layout David Edmondson
2021-05-20 14:56 ` [RFC PATCH 5/7] target/i386: Introduce AMD X86XSaveArea sub-union David Edmondson
2021-05-20 14:56 ` [RFC PATCH 6/7] target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd David Edmondson
2021-05-20 14:56 ` [RFC PATCH 7/7] target/i386: Manipulate only AMD XSAVE state on AMD David Edmondson
2021-05-20 15:15 ` [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM no-reply
2021-06-08 8:24 ` David Edmondson
2021-07-01 21:24 ` Babu Moger [this message]
2021-07-01 21:32 ` David Edmondson
2021-06-11 16:01 ` Paolo Bonzini
2021-06-14 16:21 ` David Edmondson
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