From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: liweiwei@iscas.ac.cn, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com
Subject: Re: [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string
Date: Fri, 21 Jul 2023 09:37:25 +0800 [thread overview]
Message-ID: <38a4d06e-3923-c995-5ae6-f09a6e986684@iscas.ac.cn> (raw)
In-Reply-To: <20230720132424.371132-2-dbarboza@ventanamicro.com>
On 2023/7/20 21:24, Daniel Henrique Barboza wrote:
> zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
> Add a riscv,isa string for it.
>
> Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties")
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Weiwei Li
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9339c0241d..d64ac07558 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -88,6 +88,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
> ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
> ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
> + ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
> ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
> ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
> ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
next prev parent reply other threads:[~2023-07-21 1:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 13:24 [PATCH 0/2] target/riscv: add missing riscv,isa strings Daniel Henrique Barboza
2023-07-20 13:24 ` [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string Daniel Henrique Barboza
2023-07-21 1:37 ` Weiwei Li [this message]
2023-07-23 22:40 ` Alistair Francis
2023-07-20 13:24 ` [PATCH 2/2] target/riscv/cpu.c: add smepmp " Daniel Henrique Barboza
2023-07-21 1:37 ` Weiwei Li
2023-07-23 22:41 ` Alistair Francis
2023-07-24 2:49 ` Alistair Francis
2023-07-24 2:51 ` [PATCH 0/2] target/riscv: add missing riscv,isa strings Alistair Francis
2023-07-24 12:12 ` Daniel Henrique Barboza
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