From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
alistair23@gmail.com
Subject: [PATCH v3 3/8] target/riscv: Add the ePMP feature
Date: Tue, 13 Apr 2021 12:42:09 +1000 [thread overview]
Message-ID: <3a2615d3f1433a025c7035673f66e4b72cb22878.1618281655.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1618281655.git.alistair.francis@wdc.com>
The spec is avaliable at:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 842d3ab810..13a08b86f6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,6 +81,7 @@
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
+ RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA
};
--
2.31.1
next prev parent reply other threads:[~2021-04-13 2:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-13 2:41 [PATCH v3 0/8] RISC-V: Add support for ePMP v0.9.1 Alistair Francis
2021-04-13 2:41 ` [PATCH v3 1/8] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-04-13 2:41 ` [PATCH v3 2/8] target/riscv: Define ePMP mseccfg Alistair Francis
2021-04-13 2:42 ` Alistair Francis [this message]
2021-04-13 2:42 ` [PATCH v3 4/8] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-04-13 2:42 ` [PATCH v3 5/8] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-04-14 7:35 ` Bin Meng
2021-04-15 4:17 ` Alistair Francis
2021-04-13 2:42 ` [PATCH v3 6/8] target/riscv: Add a config option for ePMP Alistair Francis
2021-04-13 2:42 ` [PATCH v3 7/8] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-04-13 2:43 ` [PATCH v3 8/8] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
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