Re: [PATCH] target/arm: Make number of counters in PMCR follow the CPU

[Richard Henderson <richard.henderson@linaro.org>]

On 5/13/22 05:28, Peter Maydell wrote:
> Currently we give all the v7-and-up CPUs a PMU with 4 counters.  This
> means that we don't provide the 6 counters that are required by the
> Arm BSA (Base System Architecture) specification if the CPU supports
> the Virtualization extensions.
> 
> Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
> specify the PMCR reset value (obtained from the appropriate TRM), and
> use the 'N' field of that value to define the number of counters
> provided.
> 
> This means that we now supply 6 counters instead of 4 for:
>   Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72,
>   Cortex-A76, Neoverse-N1, '-cpu max'
> These CPUs remain with 4 counters:
>   Cortex-A7, Cortex-A8
> This CPU goes down from 4 to 3 counters:
>   Cortex-R5
> 
> TODO: A64FX -- I don't know the correct PMCR_EL0 reset value.
> 
> Note that because we now use the PMCR reset value of the specific
> implementation, we no longer set the LC bit out of reset.  This has
> an UNKNOWN value out of reset for all cores with any AArch32 support,
> so guest software should be setting it anyway if it wants it.
> 
> This change was originally landed in commit f7fb73b8cdd3f7 (during
> the 6.0 release cycle) but was then reverted by commit
> 21c2dd77a6aa517 before that release because it did not work with KVM.
> This version fixes that by creating the scratch vCPU in
> kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature
> if KVM supports it, and then only asking KVM for the PMCR_EL0 value
> if the vCPU has a PMU.
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> I'd forgotten that we'd dropped this fix in the 6.0 timeframe
> and never picked it back up again until Alex reminded me of it...
> 
> Changes since original attempt:
>   -- rebased
>   -- fix the code in kvm_arm_get_host_cpu_features() that reads PMCR_EL0
>   -- set PMCR value for new CPUs cortex-a76, neoverse-n1
>   -- set PMCR value for now-separated-out aarch32 -cpu max
>   -- TODO comment for a64fx
> 
> Shuuichirou, Itaru: this is another patch where we need to know
> an A64FX register value...
> ---

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~