From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
Date: Mon, 5 Apr 2021 08:10:35 -0700 [thread overview]
Message-ID: <81cbeace-c357-1ef3-1a1c-f1b266e66a98@linaro.org> (raw)
In-Reply-To: <7efb55362999a5b709ea8e7fa0ea188e740d9c67.1617393702.git.alistair.francis@wdc.com>
On 4/2/21 1:02 PM, Alistair Francis wrote:
> @@ -369,6 +369,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
> static void mark_fs_dirty(DisasContext *ctx)
> {
> TCGv tmp;
> + CPUState *cpu = ctx->cs;
> + CPURISCVState *env = cpu->env_ptr;
> +
> if (ctx->mstatus_fs == MSTATUS_FS) {
> return;
> }
> @@ -377,12 +380,24 @@ static void mark_fs_dirty(DisasContext *ctx)
>
> tmp = tcg_temp_new();
> tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
> - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
> + if (riscv_cpu_is_32bit(env)) {
This is less than ideal, and will be incorrect long term.
You should check ctx->misa instead.
Eventually you'll need to change riscv_tr_init_disas_context to not just copy
ctx->misa from env. At present we flush all translation blocks when misa
changes, which works. But you won't want to do that when the hypervisor is
64-bit and the guest is 32-bit.
Anyway, I think it would be a good idea to create a helper local to translate,
akin to has_ext().
> + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS32_SD);
> + } else {
> +#if defined(TARGET_RISCV64)
> + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS64_SD);
> +#endif
The ifdefs are ugly. I presume there's some sort of compiler warning here?
Does it go away if you cast to target_ulong?
How about
target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
r~
next prev parent reply other threads:[~2021-04-05 15:25 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-02 20:02 [PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-02 20:02 ` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-05 14:48 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-05 14:49 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-05 14:54 ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-05 15:10 ` Richard Henderson [this message]
2021-04-07 17:11 ` Alistair Francis
2021-04-08 15:20 ` Alistair Francis
2021-04-08 18:51 ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-05 15:14 ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-05 15:15 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-05 15:15 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:03 ` [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build Alistair Francis
2021-04-06 14:57 ` Richard Henderson
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