Re: [PATCH] target/riscv: Add missing include guard in pmu.h

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: frank.chang@sifive.com, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Weiwei Li <liwei1518@gmail.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH] target/riscv: Add missing include guard in pmu.h
Date: Tue, 20 Feb 2024 13:20:22 -0300	[thread overview]
Message-ID: <9df86826-44c2-4816-ae59-189773c51d95@ventanamicro.com> (raw)
In-Reply-To: <20240220110907.10479-1-frank.chang@sifive.com>


On 2/20/24 08:08, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Add missing include guard in pmu.h to avoid the problem of double
> inclusion.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/pmu.h | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
> index 505fc850d3..7c0ad661e0 100644
> --- a/target/riscv/pmu.h
> +++ b/target/riscv/pmu.h
> @@ -16,6 +16,9 @@
>    * this program.  If not, see <http://www.gnu.org/licenses/>.
>    */
>   
> +#ifndef RISCV_PMU_H
> +#define RISCV_PMU_H
> +
>   #include "cpu.h"
>   #include "qapi/error.h"
>   
> @@ -31,3 +34,5 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
>   void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
>   int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
>                             uint32_t ctr_idx);
> +
> +#endif /* RISCV_PMU_H */