From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding
Date: Thu, 30 May 2019 11:36:46 +0800 [thread overview]
Message-ID: <CAEUhbmXLr3zXhbphXRvqfyW1FH9qo3yoPwnFoRoYNtbwkrBBKw@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKNAL8KtVgfCx6yhaNYEL=_wnZ5Vf1eSjxwtg0x6_q+UHw@mail.gmail.com>
Hi Alistair,
On Thu, May 30, 2019 at 11:14 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, May 29, 2019 at 1:52 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > The largest pci bus number should be calculated from ECAM size,
> > instead of its base address.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> This seems ok, can you maybe explain what this fixes?
>
The logic is wrong, as the commit message said. With current wrong
logic, the largest pci bus number encoded in "bus-ranges" property was
wrongly set to 0x2ff in this case. Per pci spec, the bus number should
not exceed 0xff.
Regards,
Bin
next prev parent reply other threads:[~2019-05-30 3:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-29 8:52 [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding Bin Meng
2019-05-30 3:13 ` Alistair Francis
2019-05-30 3:36 ` Bin Meng [this message]
2019-06-06 12:55 ` Bin Meng
2019-06-06 18:43 ` Alistair Francis
2019-06-26 1:47 ` Bin Meng
2019-06-26 8:01 ` Palmer Dabbelt
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