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From: Chih-Min Chao <chihmin.chao@sifive.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Alistair Francis <alistair23@gmail.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH-4.2 v2 4/5] target/riscv: Update the Hypervisor CSRs to v0.4
Date: Mon, 5 Aug 2019 14:19:16 +0800	[thread overview]
Message-ID: <CAEiOBXVxn+AXX0M4U_mYzfHVjTECoCUxmPLpUZBFDXCB4i-gXQ@mail.gmail.com> (raw)
In-Reply-To: <dc666f1d37590b76d66415941bc24fe5a7cb46b4.1564529681.git.alistair.francis@wdc.com>

On Wed, Jul 31, 2019 at 7:40 AM Alistair Francis <alistair.francis@wdc.com>
wrote:

> Update the Hypervisor CSR addresses to match the v0.4 spec.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu_bits.h | 35 ++++++++++++++++++-----------------
>  1 file changed, 18 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 11f971ad5d..e99834856c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -173,6 +173,24 @@
>  #define CSR_SPTBR           0x180
>  #define CSR_SATP            0x180
>
> +/* Hpervisor CSRs */
> +#define CSR_HSTATUS         0x600
> +#define CSR_HEDELEG         0x602
> +#define CSR_HIDELEG         0x603
> +#define CSR_HCOUNTERNEN     0x606
> +#define CSR_HGATP           0x680
> +
> +#if defined(TARGET_RISCV32)
> +#define HGATP_MODE           SATP32_MODE
> +#define HGATP_VMID           SATP32_ASID
> +#define HGATP_PPN            SATP32_PPN
> +#endif
> +#if defined(TARGET_RISCV64)
> +#define HGATP_MODE           SATP64_MODE
> +#define HGATP_VMID           SATP64_ASID
> +#define HGATP_PPN            SATP64_PPN
> +#endif
> +
>  /* Physical Memory Protection */
>  #define CSR_PMPCFG0         0x3a0
>  #define CSR_PMPCFG1         0x3a1
> @@ -206,23 +224,6 @@
>  #define CSR_DPC             0x7b1
>  #define CSR_DSCRATCH        0x7b2
>
> -/* Hpervisor CSRs */
> -#define CSR_HSTATUS         0xa00
> -#define CSR_HEDELEG         0xa02
> -#define CSR_HIDELEG         0xa03
> -#define CSR_HGATP           0xa80
> -
> -#if defined(TARGET_RISCV32)
> -#define HGATP_MODE           SATP32_MODE
> -#define HGATP_ASID           SATP32_ASID
> -#define HGATP_PPN            SATP32_PPN
> -#endif
> -#if defined(TARGET_RISCV64)
> -#define HGATP_MODE           SATP64_MODE
> -#define HGATP_ASID           SATP64_ASID
> -#define HGATP_PPN            SATP64_PPN
> -#endif
> -
>  /* Performance Counters */
>  #define CSR_MHPMCOUNTER3    0xb03
>  #define CSR_MHPMCOUNTER4    0xb04
> --
> 2.22.0
>
> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>

  reply	other threads:[~2019-08-05  6:19 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-30 23:35 [Qemu-devel] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 1/5] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 2/5] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 3/5] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-08-05  6:59   ` Chih-Min Chao
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 4/5] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-08-05  6:19   ` Chih-Min Chao [this message]
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names Alistair Francis
2019-08-12 23:08   ` Palmer Dabbelt
2019-08-13 17:06     ` Alistair Francis
2019-08-14 18:07       ` Palmer Dabbelt

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