From: Chih-Min Chao <chihmin.chao@sifive.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [Qemu-devel] [Qemu-riscv] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
Date: Mon, 5 Aug 2019 14:14:07 +0800 [thread overview]
Message-ID: <CAEiOBXWQ02uRQQOpP=Rauq8WZnYtoxNqjM--Rpi5tHX2W0bGsw@mail.gmail.com> (raw)
In-Reply-To: <1564792052-6469-1-git-send-email-bmeng.cn@gmail.com>
On Sat, Aug 3, 2019 at 8:27 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> Some of the SoC IP block sizes are wrong. Correct them according
> to the FE310 manual.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> hw/riscv/sifive_e.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 2a499d8..9655847 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -53,13 +53,13 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } sifive_e_memmap[] = {
> - [SIFIVE_E_DEBUG] = { 0x0, 0x100 },
> + [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
> [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
> [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
> [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
> [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
> - [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
> - [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
> + [SIFIVE_E_AON] = { 0x10000000, 0x1000 },
> + [SIFIVE_E_PRCI] = { 0x10008000, 0x1000 },
> [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
> [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
> [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
> --
> 2.7.4
>
>
It seems the modification follows E310-G002(Hifive1 Rev B) spec and the
origin is for E310-G000(Hifive1) spec.
There should be some way to specify different board version with different
memory map or we have policy, always support the latest spec.
chihmin
next prev parent reply other threads:[~2019-08-05 6:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-03 0:27 [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes Bin Meng
2019-08-05 6:14 ` Chih-Min Chao [this message]
2019-08-05 6:43 ` [Qemu-devel] [Qemu-riscv] " Bin Meng
2019-08-06 21:06 ` Philippe Mathieu-Daudé
2019-08-07 1:36 ` Bin Meng
2019-08-07 2:53 ` Bin Meng
2019-08-14 9:34 ` Bin Meng
2019-09-04 3:41 ` Bin Meng
2019-09-04 18:34 ` Palmer Dabbelt
2020-06-23 6:35 ` Bin Meng
2020-06-23 16:07 ` Alistair Francis
2019-08-05 17:51 ` [Qemu-devel] " Alistair Francis
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