From: Peter Maydell <peter.maydell@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-devel@nongnu.org, f4bug@amsat.org, mads@ynddal.dk,
qemu-arm@nongnu.org,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Subject: Re: [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs
Date: Mon, 26 Sep 2022 16:30:48 +0100 [thread overview]
Message-ID: <CAFEAcA9NeO2MZpybhA8voH-3o5k9Cqa4EOg-0nk91gzQ9JJrPQ@mail.gmail.com> (raw)
In-Reply-To: <87h70u40ql.fsf@linaro.org>
On Mon, 26 Sept 2022 at 16:24, Alex Bennée <alex.bennee@linaro.org> wrote:
>
>
> Peter Maydell <peter.maydell@linaro.org> writes:
> > I still don't see anything in this patchset that updates
> > the code which currently assumes requester_id to be a PCI
> > index to check that it hasn't been handed a MemTxAttrs
> > that uses requester_id as a CPU number.
>
> OK I'll update so all the existing cases setting requester_id also set
> the type to MEMTXATTRS_MSI.
The problem is not the places that set requester_id (you can
arrange for the default to be MSI for back-compat if you don't
want to explicitly set it), but the places that *read* it.
-- PMM
next prev parent reply other threads:[~2022-09-26 16:01 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-26 13:38 [PATCH v2 00/11] gdbstub/next (MemTxAttrs and re-factoring) Alex Bennée
2022-09-26 13:38 ` [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-09-26 14:34 ` Peter Maydell
2022-09-26 15:09 ` Alex Bennée
2022-09-26 15:30 ` Peter Maydell [this message]
2022-09-26 20:15 ` Alexander Graf
2022-09-26 13:38 ` [PATCH v2 02/11] target/arm: enable tracking of " Alex Bennée
2022-09-26 14:12 ` Peter Maydell
2022-09-26 15:05 ` Alex Bennée
2022-09-26 15:07 ` Peter Maydell
2022-09-26 13:38 ` [PATCH v2 03/11] target/arm: ensure HVF traps set appropriate MemTxAttrs Alex Bennée
2022-09-26 14:10 ` Peter Maydell
2022-09-26 15:46 ` Alex Bennée
2022-09-26 20:19 ` Alexander Graf
2022-09-26 13:38 ` [PATCH v2 04/11] qtest: make read/write operation appear to be from CPU Alex Bennée
2022-09-27 9:45 ` Thomas Huth
2022-09-26 13:38 ` [PATCH v2 05/11] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-09-26 14:14 ` Peter Maydell
2022-09-26 15:06 ` Alex Bennée
2022-09-26 15:18 ` Peter Maydell
2022-09-26 15:41 ` Alex Bennée
2022-09-26 15:45 ` Peter Maydell
2022-09-26 13:38 ` [PATCH v2 06/11] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-09-26 13:39 ` [PATCH v2 07/11] configure: move detected gdb to TCG's config-host.mak Alex Bennée
2022-09-26 13:39 ` [PATCH v2 08/11] gdbstub: move into its own sub directory Alex Bennée
2022-09-26 13:39 ` [PATCH v2 09/11] gdbstub: move sstep flags probing into AccelClass Alex Bennée
2022-09-26 13:39 ` [PATCH v2 10/11] gdbstub: move breakpoint logic to accel ops Alex Bennée
2022-09-26 13:39 ` [PATCH v2 11/11] gdbstub: move guest debug support check to ops Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAFEAcA9NeO2MZpybhA8voH-3o5k9Cqa4EOg-0nk91gzQ9JJrPQ@mail.gmail.com \
--to=peter.maydell@linaro.org \
--cc=alex.bennee@linaro.org \
--cc=edgar.iglesias@gmail.com \
--cc=f4bug@amsat.org \
--cc=mads@ynddal.dk \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).