From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aSopp-0004Pe-5Z for qemu-devel@nongnu.org; Mon, 08 Feb 2016 11:38:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aSopj-0008Ds-Sz for qemu-devel@nongnu.org; Mon, 08 Feb 2016 11:38:40 -0500 Received: from mail-vk0-x22c.google.com ([2607:f8b0:400c:c05::22c]:35180) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aSopi-0008CR-La for qemu-devel@nongnu.org; Mon, 08 Feb 2016 11:38:39 -0500 Received: by mail-vk0-x22c.google.com with SMTP id e6so98711852vkh.2 for ; Mon, 08 Feb 2016 08:38:38 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <56B8C2EE.5090700@gmail.com> References: <1454690704-16233-1-git-send-email-peter.maydell@linaro.org> <1454690704-16233-6-git-send-email-peter.maydell@linaro.org> <56B8C2EE.5090700@gmail.com> From: Peter Maydell Date: Mon, 8 Feb 2016 16:38:18 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH 5/6] target-arm: Implement MDCR_EL2.TDA and MDCR_EL2.TDA traps List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Fedorov Cc: "Edgar E. Iglesias" , qemu-arm , QEMU Developers , Patch Tracking On 8 February 2016 at 16:31, Sergey Fedorov wrote: > One of the MDCR_EL2's should be MDCR_EL3 instead. Oops, yes :-) > On 05.02.2016 19:45, Peter Maydell wrote: >> Implement the debug register traps controlled by MDCR_EL2.TDA >> and MDCR_EL3.TDA. >> >> Signed-off-by: Peter Maydell >> --- >> target-arm/helper.c | 39 ++++++++++++++++++++++++++++++--------- >> 1 file changed, 30 insertions(+), 9 deletions(-) >> >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 8c2adbc..064b415 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -420,6 +420,24 @@ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, >> return CP_ACCESS_OK; >> } >> >> +/* Check for traps to general debug registers, which are controlled >> + * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. >> + */ >> +static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, >> + bool isread) >> +{ >> + int el = arm_current_el(env); >> + >> + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) >> + && !arm_is_secure_below_el3(env)) { >> + return CP_ACCESS_TRAP_EL2; >> + } >> + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { >> + return CP_ACCESS_TRAP_EL3; >> + } >> + return CP_ACCESS_OK; >> +} >> + >> static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) >> { >> ARMCPU *cpu = arm_env_get_cpu(env); >> @@ -3385,7 +3403,8 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { >> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >> { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, >> .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, >> - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >> + .access = PL2_RW, .accessfn = access_tda, >> + .type = ARM_CP_CONST, .resetvalue = 0 }, >> { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, >> .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >> .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, >> @@ -3804,7 +3823,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { >> /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ >> { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, >> .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, >> - .access = PL1_RW, >> + .access = PL1_RW, .accessfn = access_tda, >> .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), >> .resetvalue = 0 }, >> /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. >> @@ -3813,7 +3832,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { >> { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, >> .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, >> .type = ARM_CP_ALIAS, >> - .access = PL1_R, >> + .access = PL1_R, .accessfn = access_tda, > > From ARMv8 ARM rev. A.h: "If MDSCR_EL1.TDCC==1, EL0 read accesses to > this register are trapped to EL1." But it seems like we just don't > implement "Config-RO for EL0" so far. Yes. There's a comment about this, though it's just outside the context region that diff has produced. > Maybe it's worth to implement a > separate function for checks controlled by MDSCR_EL1.TDCC? I think that's a separate issue from the EL2/EL3 traps and should go in its own patch. This series is just trying to get EL3 right. thanks -- PMM