21:18 Sre, 25.03.2020. Philippe Mathieu-Daudé је написао/ла: > > Running the coccinelle script produced: > > $ spatch \ > --macro-file scripts/cocci-macro-file.h --include-headers \ > --sp-file scripts/coccinelle/object_property_missing_error_propagate.cocci \ > --keep-comments --smpl-spacing --dir hw > > [[manual check required: error_propagate() might be missing in object_property_set_int() hw/mips/boston.c:462:4]] > [[manual check required: error_propagate() might be missing in object_property_set_str() hw/mips/boston.c:460:4]] > > Since the uses are inside a MachineClass::init() function, > directly use &error_fatal instead of error_propagate(). > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/mips/boston.c | 17 ++++++----------- > 1 file changed, 6 insertions(+), 11 deletions(-) > > diff --git a/hw/mips/boston.c b/hw/mips/boston.c > index 98ecd25e8e..2e821ca7d6 100644 > --- a/hw/mips/boston.c > +++ b/hw/mips/boston.c > @@ -425,121 +425,116 @@ xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, > static void boston_mach_init(MachineState *machine) > { > DeviceState *dev; > BostonState *s; > - Error *err = NULL; > MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; > MemoryRegion *sys_mem = get_system_memory(); > XilinxPCIEHost *pcie2; > PCIDevice *ahci; > DriveInfo *hd[6]; > Chardev *chr; > int fw_size, fit_err; > bool is_64b; > > if ((machine->ram_size % GiB) || > (machine->ram_size > (2 * GiB))) { > error_report("Memory size must be 1GB or 2GB"); > exit(1); > } > > dev = qdev_create(NULL, TYPE_MIPS_BOSTON); > qdev_init_nofail(dev); > > s = BOSTON(dev); > s->mach = machine; > > if (!cpu_supports_cps_smp(machine->cpu_type)) { > error_report("Boston requires CPUs which support CPS"); > exit(1); > } > > is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); > > sysbus_init_child_obj(OBJECT(machine), "cps", OBJECT(&s->cps), > sizeof(s->cps), TYPE_MIPS_CPS); > object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", > - &err); > - object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp", &err); > - object_property_set_bool(OBJECT(&s->cps), true, "realized", &err); > - > - if (err != NULL) { > - error_report("%s", error_get_pretty(err)); > - exit(1); > - } > - > + &error_fatal); > + object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp", > + &error_fatal); > + object_property_set_bool(OBJECT(&s->cps), true, "realized", &error_fatal); > sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); > > flash = g_new(MemoryRegion, 1); > - memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err); > + memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, > + &error_fatal); > memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); > > memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0); > > ddr_low_alias = g_new(MemoryRegion, 1); > memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", > machine->ram, 0, > MIN(machine->ram_size, (256 * MiB))); > memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); > > xilinx_pcie_init(sys_mem, 0, > 0x10000000, 32 * MiB, > 0x40000000, 1 * GiB, > get_cps_irq(&s->cps, 2), false); > > xilinx_pcie_init(sys_mem, 1, > 0x12000000, 32 * MiB, > 0x20000000, 512 * MiB, > get_cps_irq(&s->cps, 1), false); > > pcie2 = xilinx_pcie_init(sys_mem, 2, > 0x14000000, 32 * MiB, > 0x16000000, 1 * MiB, > get_cps_irq(&s->cps, 0), true); > > platreg = g_new(MemoryRegion, 1); > memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, > "boston-platregs", 0x1000); > memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); > > s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, > get_cps_irq(&s->cps, 3), 10000000, > serial_hd(0), DEVICE_NATIVE_ENDIAN); > > lcd = g_new(MemoryRegion, 1); > memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); > memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); > > chr = qemu_chr_new("lcd", "vc:320x240", NULL); > qemu_chr_fe_init(&s->lcd_display, chr, NULL); > qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, > boston_lcd_event, NULL, s, NULL, true); > > ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, > PCI_DEVFN(0, 0), > true, TYPE_ICH9_AHCI); > g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); > ide_drive_get(hd, ahci_get_num_ports(ahci)); > ahci_ide_create_devs(ahci, hd); > > if (machine->firmware) { > fw_size = load_image_targphys(machine->firmware, > 0x1fc00000, 4 * MiB); > if (fw_size == -1) { > error_report("unable to load firmware image '%s'", > machine->firmware); > exit(1); > } > } else if (machine->kernel_filename) { > fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); > if (fit_err) { > error_report("unable to load FIT image"); > exit(1); > } > > gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, > s->kernel_entry, s->fdt_base, is_64b); > } else if (!qtest_enabled()) { > error_report("Please provide either a -kernel or -bios argument"); > exit(1); > } > } > -- > 2.21.1 > Reviewed-by: Aleksandar Markovic