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From: Alistair Francis <alistair23@gmail.com>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org,  mst@redhat.com, imammedo@redhat.com,
	anisinha@redhat.com,  peter.maydell@linaro.org,
	shannon.zhaosl@gmail.com, sunilvl@ventanamicro.com,
	 palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com,  liwei1518@gmail.com,
	dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH v2 2/2] hw/riscv/virt-acpi-build.c: Generate SPCR table
Date: Thu, 15 Feb 2024 13:29:42 +1000	[thread overview]
Message-ID: <CAKmqyKMNma6GM6xBMH7Ywbb1CxkbyACK0yx+8jYoGqdGd=4AzQ@mail.gmail.com> (raw)
In-Reply-To: <20240116010930.43433-3-jeeheng.sia@starfivetech.com>

On Tue, Jan 16, 2024 at 11:11 AM Sia Jee Heng
<jeeheng.sia@starfivetech.com> wrote:
>
> Generate Serial Port Console Redirection Table (SPCR) for RISC-V
> virtual machine.
>
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/virt-acpi-build.c | 39 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 26c7e4482d..7fc5071c84 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -174,6 +174,42 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
>      aml_append(scope, dev);
>  }
>
> +/*
> + * Serial Port Console Redirection Table (SPCR)
> + * Rev: 1.07
> + */
> +
> +static void
> +spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
> +{
> +    AcpiSpcrData serial = {
> +        .interface_type = 0,       /* 16550 compatible */
> +        .base_addr.id = AML_AS_SYSTEM_MEMORY,
> +        .base_addr.width = 32,
> +        .base_addr.offset = 0,
> +        .base_addr.size = 1,
> +        .base_addr.addr = s->memmap[VIRT_UART0].base,
> +        .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */
> +        .pc_interrupt = 0,
> +        .interrupt = UART0_IRQ,
> +        .baud_rate = 7,            /* 15200 */
> +        .parity = 0,
> +        .stop_bits = 1,
> +        .flow_control = 0,
> +        .terminal_type = 3,        /* ANSI */
> +        .language = 0,             /* Language */
> +        .pci_device_id = 0xffff,   /* not a PCI device*/
> +        .pci_vendor_id = 0xffff,   /* not a PCI device*/
> +        .pci_bus = 0,
> +        .pci_device = 0,
> +        .pci_function = 0,
> +        .pci_flags = 0,
> +        .pci_segment = 0,
> +    };
> +
> +    build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
> +}
> +
>  /* RHCT Node[N] starts at offset 56 */
>  #define RHCT_NODE_ARRAY_OFFSET 56
>
> @@ -555,6 +591,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
>      acpi_add_table(table_offsets, tables_blob);
>      build_rhct(tables_blob, tables->linker, s);
>
> +    acpi_add_table(table_offsets, tables_blob);
> +    spcr_setup(tables_blob, tables->linker, s);
> +
>      acpi_add_table(table_offsets, tables_blob);
>      {
>          AcpiMcfgInfo mcfg = {
> --
> 2.34.1
>
>


  reply	other threads:[~2024-02-15  3:30 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-16  1:09 [PATCH v2 0/2] RISC-V: ACPI: Enable SPCR Sia Jee Heng
2024-01-16  1:09 ` [PATCH v2 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location Sia Jee Heng
2024-02-15  3:26   ` Alistair Francis
2024-03-06 18:57   ` Daniel Henrique Barboza
2024-03-06 20:00     ` Daniel Henrique Barboza
2024-03-07  1:33     ` Alistair Francis
2024-03-07  1:42       ` JeeHeng Sia
2024-03-07  3:45       ` Sunil V L
2024-03-07  9:22         ` Daniel Henrique Barboza
2024-03-20  4:41           ` Alistair Francis
2024-01-16  1:09 ` [PATCH v2 2/2] hw/riscv/virt-acpi-build.c: Generate SPCR table Sia Jee Heng
2024-02-15  3:29   ` Alistair Francis [this message]
2024-02-15  9:54 ` [PATCH v2 0/2] RISC-V: ACPI: Enable SPCR Alistair Francis

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