From: Alistair Francis <alistair23@gmail.com>
To: Rajnesh Kanwal <rkanwal@rivosinc.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com,
apatel@ventanamicro.com
Subject: Re: [PATCH v2 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
Date: Fri, 2 Jun 2023 13:13:32 +1000 [thread overview]
Message-ID: <CAKmqyKN1z3H4-wpY1SZLEDAu5EoMAg3zuvz9rydm-XNMujaJ6g@mail.gmail.com> (raw)
In-Reply-To: <20230526162308.22892-3-rkanwal@rivosinc.com>
On Sat, May 27, 2023 at 2:24 AM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
> as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
> async flag check is performed before invoking semihosting logic.
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 57d04385f1..b25ee179e9 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1602,15 +1602,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong htval = 0;
> target_ulong mtval2 = 0;
>
> - if (cause == RISCV_EXCP_SEMIHOST) {
> - do_common_semihosting(cs);
> - env->pc += 4;
> - return;
> - }
> -
> if (!async) {
> /* set tval to badaddr for traps with address information */
> switch (cause) {
> + case RISCV_EXCP_SEMIHOST:
> + do_common_semihosting(cs);
> + env->pc += 4;
> + return;
> case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
> case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
> case RISCV_EXCP_LOAD_ADDR_MIS:
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2023-06-02 3:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 16:23 [PATCH v2 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support Rajnesh Kanwal
2023-05-26 16:23 ` [PATCH v2 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie Rajnesh Kanwal
2023-06-02 3:10 ` Alistair Francis
2023-05-26 16:23 ` [PATCH v2 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST Rajnesh Kanwal
2023-06-02 3:13 ` Alistair Francis [this message]
2023-05-26 16:23 ` [PATCH v2 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled Rajnesh Kanwal
2023-06-02 3:17 ` Alistair Francis
2023-05-26 16:23 ` [PATCH v2 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip Rajnesh Kanwal
2023-06-02 3:26 ` Alistair Francis
2023-05-26 16:23 ` [PATCH v2 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support Rajnesh Kanwal
2023-06-30 9:26 ` Daniel Henrique Barboza
2023-05-26 16:23 ` [PATCH v2 6/6] target/riscv: Add HS-mode " Rajnesh Kanwal
2023-06-30 9:33 ` Daniel Henrique Barboza
2023-09-06 14:38 ` [PATCH v2 0/6] target/riscv: Add RISC-V Virtual IRQs " Daniel Henrique Barboza
2023-09-21 6:29 ` Rajnesh Kanwal
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