From: Alistair Francis <alistair23@gmail.com>
To: Rob Bradford <rbradford@rivosinc.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
atishp@rivosinc.com, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH] target/riscv: Check for 'A' extension on all atomic instructions
Date: Thu, 11 Jan 2024 16:15:56 +1000 [thread overview]
Message-ID: <CAKmqyKO54ohZcQdgB3TFahRdCFm9wtBBKK-fPOguHWGp37SoXQ@mail.gmail.com> (raw)
In-Reply-To: <20240110163959.31291-1-rbradford@rivosinc.com>
On Thu, Jan 11, 2024 at 3:44 AM Rob Bradford <rbradford@rivosinc.com> wrote:
>
> Add requirement that 'A' is enabled for all atomic instructions that
> lack the check. This makes the 64-bit versions consistent with the
> 32-bit versions in the same file.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
> index 5f194a447b..f0368de3e4 100644
> --- a/target/riscv/insn_trans/trans_rva.c.inc
> +++ b/target/riscv/insn_trans/trans_rva.c.inc
> @@ -163,65 +163,76 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
> static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_lr(ctx, a, MO_ALIGN | MO_TEUQ);
> }
>
> static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_sc(ctx, a, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEUQ));
> }
>
> static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
> {
> REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVA);
> return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEUQ));
> }
> --
> 2.43.0
>
>
prev parent reply other threads:[~2024-01-11 6:17 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-10 16:39 [PATCH] target/riscv: Check for 'A' extension on all atomic instructions Rob Bradford
2024-01-10 18:55 ` Daniel Henrique Barboza
2024-01-11 3:55 ` Alistair Francis
2024-01-11 6:15 ` Alistair Francis [this message]
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