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X-Received-From: 2a00:1450:4864:20::143 Subject: Re: [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Aug 15, 2019 at 2:38 PM Alistair Francis wrote: > > The mip register is an MXLEN-bit long register. Convert it to a > target_ulong type instead of uint32_t. > > Signed-off-by: Alistair Francis MIP is 32-bit to allow atomic access on 32-bit hosts, so I am going to send a v4 with this patch dropped. Alistair > --- > target/riscv/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 2dc9b17678..0a7985c3f7 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -130,7 +130,7 @@ struct CPURISCVState { > * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. > * mip is 32-bits to allow atomic_read on 32-bit hosts. > */ > - uint32_t mip; > + target_ulong mip; > uint32_t miclaim; > > target_ulong mie; > -- > 2.22.0 >