From: Alistair Francis <alistair23@gmail.com>
To: Michael Tokarev <mjt@tls.msk.ru>
Cc: qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/60] riscv-to-apply queue
Date: Thu, 15 Jun 2023 14:03:44 +1000 [thread overview]
Message-ID: <CAKmqyKPT9-Ru+AHhQR-N+2EctyWCdDY5nErT5Z0GbJ+zJfEcYw@mail.gmail.com> (raw)
In-Reply-To: <6693132a-c820-5d04-6f9f-ac38d067e935@tls.msk.ru>
On Wed, Jun 14, 2023 at 10:17 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 14.06.2023 04:19, Alistair Francis wrote:
> > The following changes since commit fdd0df5340a8ebc8de88078387ebc85c5af7b40f:
> >
> > Merge tag 'pull-ppc-20230610' of https://gitlab.com/danielhb/qemu into staging (2023-06-10 07:25:00 -0700)
> >
> > are available in the Git repository at:
> >
> > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230614
> >
> > for you to fetch changes up to 860029321d9ebdff47e89561de61e9441fead70a:
> >
> > hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. (2023-06-14 10:04:30 +1000)
>
> Is anything there worth to apply to -stable?
>
> I picked this one:
> hw/riscv: qemu crash when NUMA nodes exceed available CPUs
Thanks for that!
>
> Anything else?
I don't think there is anything else, the other fixes are mostly for
experimental features, so I don't think we need to backport them.
Alistair
>
> Thanks!
>
> /mjt
>
> > Daniel Henrique Barboza (10):
> > target/riscv/vector_helper.c: skip set tail when vta is zero
> > target/riscv/cpu.c: add riscv_cpu_validate_v()
> > target/riscv/cpu.c: remove set_vext_version()
> > target/riscv/cpu.c: remove set_priv_version()
> > target/riscv: add PRIV_VERSION_LATEST
> > target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
> > target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
> > target/riscv/cpu.c: validate extensions before riscv_timer_init()
> > target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
> > target/riscv: rework write_misa()
> >
> > Himanshu Chauhan (1):
> > target/riscv: Smepmp: Return error when access permission not allowed in PMP
> >
> > Ivan Klokov (1):
> > util/log: Add vector registers to log
> >
> > Mayuresh Chitale (3):
> > target/riscv: smstateen check for fcsr
> > target/riscv: Reuse tb->flags.FS
> > target/riscv: smstateen knobs
> >
> > Philippe Mathieu-Daudé (5):
> > hw/riscv/opentitan: Rename machine_[class]_init() functions
> > hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
> > hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
> > hw/riscv/opentitan: Explicit machine type definition
> > hw/riscv/opentitan: Correct OpenTitanState parent type/size
> >
> > Sunil V L (3):
> > hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
> > riscv/virt: Support using pflash via -blockdev option
> > docs/system: riscv: Add pflash usage details
> >
> > Tommy Wu (1):
> > hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
> >
> > Weiwei Li (33):
> > target/riscv: Move zc* out of the experimental properties
> > target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version
> > target/riscv: Update check for Zca/Zcf/Zcd
> > target/riscv: Update pmp_get_tlb_size()
> > target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
> > target/riscv: Make the short cut really work in pmp_hart_has_privs
> > target/riscv: Change the return type of pmp_hart_has_privs() to bool
> > target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
> > target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
> > target/riscv: Flush TLB when MMWP or MML bits are changed
> > target/riscv: Update the next rule addr in pmpaddr_csr_write()
> > target/riscv: Flush TLB when pmpaddr is updated
> > target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
> > target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
> > target/riscv: Deny access if access is partially inside the PMP entry
> > target/riscv: Fix pointer mask transformation for vector address
> > target/riscv: Update cur_pmmask/base when xl changes
> > disas: Change type of disassemble_info.target_info to pointer
> > target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
> > target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
> > disas/riscv.c: Support disas for Zcm* extensions
> > disas/riscv.c: Support disas for Z*inx extensions
> > disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
> > disas/riscv.c: Fix lines with over 80 characters
> > disas/riscv.c: Remove redundant parentheses
> > target/riscv: Fix target address to update badaddr
> > target/riscv: Introduce cur_insn_len into DisasContext
> > target/riscv: Change gen_goto_tb to work on displacements
> > target/riscv: Change gen_set_pc_imm to gen_update_pc
> > target/riscv: Use true diff for gen_pc_plus_diff
> > target/riscv: Enable PC-relative translation
> > target/riscv: Remove pc_succ_insn from DisasContext
> > target/riscv: Fix initialized value for cur_pmmask
> >
> > Xiao Wang (2):
> > target/riscv/vector_helper.c: clean up reference of MTYPE
> > target/riscv/vector_helper.c: Remove the check for extra tail elements
> >
> > Yin Wang (1):
> > hw/riscv: qemu crash when NUMA nodes exceed available CPUs
> >
> > docs/system/riscv/virt.rst | 31 +
> > include/disas/dis-asm.h | 2 +-
> > include/hw/core/cpu.h | 2 +
> > include/hw/riscv/opentitan.h | 6 +-
> > include/qemu/log.h | 1 +
> > target/riscv/cpu.h | 117 +--
> > target/riscv/cpu_cfg.h | 136 +++
> > target/riscv/pmp.h | 11 +-
> > accel/tcg/cpu-exec.c | 3 +
> > disas/riscv.c | 1194 +++++++++++++-----------
> > hw/intc/riscv_aplic.c | 4 +-
> > hw/riscv/numa.c | 6 +
> > hw/riscv/opentitan.c | 38 +-
> > hw/riscv/virt.c | 59 +-
> > target/riscv/cpu.c | 384 +++++---
> > target/riscv/cpu_helper.c | 37 +-
> > target/riscv/csr.c | 75 +-
> > target/riscv/pmp.c | 205 ++--
> > target/riscv/translate.c | 99 +-
> > target/riscv/vector_helper.c | 33 +-
> > util/log.c | 2 +
> > target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
> > target/riscv/insn_trans/trans_rvd.c.inc | 12 +-
> > target/riscv/insn_trans/trans_rvf.c.inc | 21 +-
> > target/riscv/insn_trans/trans_rvi.c.inc | 46 +-
> > target/riscv/insn_trans/trans_rvv.c.inc | 4 +-
> > target/riscv/insn_trans/trans_rvzawrs.c.inc | 2 +-
> > target/riscv/insn_trans/trans_rvzce.c.inc | 10 +-
> > target/riscv/insn_trans/trans_xthead.c.inc | 2 +-
> > 29 files changed, 1442 insertions(+), 1102 deletions(-)
> > create mode 100644 target/riscv/cpu_cfg.h
> >
>
prev parent reply other threads:[~2023-06-15 4:05 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
2023-06-14 1:19 ` [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero Alistair Francis
2023-06-14 1:19 ` [PULL 02/60] target/riscv: Move zc* out of the experimental properties Alistair Francis
2023-06-14 1:19 ` [PULL 03/60] target/riscv/cpu.c: add riscv_cpu_validate_v() Alistair Francis
2023-06-14 1:19 ` [PULL 04/60] target/riscv/cpu.c: remove set_vext_version() Alistair Francis
2023-06-14 1:19 ` [PULL 05/60] target/riscv/cpu.c: remove set_priv_version() Alistair Francis
2023-06-14 1:19 ` [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST Alistair Francis
2023-06-14 1:19 ` [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Alistair Francis
2023-06-14 1:19 ` [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd Alistair Francis
2023-06-14 1:19 ` [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Alistair Francis
2023-06-14 1:19 ` [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Alistair Francis
2023-06-14 1:19 ` [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() Alistair Francis
2023-06-14 1:19 ` [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Alistair Francis
2023-06-14 1:19 ` [PULL 13/60] target/riscv: rework write_misa() Alistair Francis
2023-06-14 1:19 ` [PULL 14/60] target/riscv: Update pmp_get_tlb_size() Alistair Francis
2023-06-14 1:19 ` [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Alistair Francis
2023-06-14 1:19 ` [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs Alistair Francis
2023-06-14 1:19 ` [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool Alistair Francis
2023-06-14 1:19 ` [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Alistair Francis
2023-06-14 1:19 ` [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Alistair Francis
2023-06-14 1:19 ` [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed Alistair Francis
2023-06-14 1:19 ` [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write() Alistair Francis
2023-06-14 1:19 ` [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated Alistair Francis
2023-06-14 1:19 ` [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Alistair Francis
2023-06-14 1:19 ` [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Alistair Francis
2023-06-14 1:19 ` [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry Alistair Francis
2023-06-14 1:19 ` [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions Alistair Francis
2023-06-14 1:19 ` [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Alistair Francis
2023-06-14 1:19 ` [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Alistair Francis
2023-06-14 1:19 ` [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition Alistair Francis
2023-06-14 1:19 ` [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size Alistair Francis
2023-06-14 1:19 ` [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs Alistair Francis
2023-06-14 1:19 ` [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address Alistair Francis
2023-06-14 1:19 ` [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes Alistair Francis
2023-06-14 1:19 ` [PULL 34/60] target/riscv: smstateen check for fcsr Alistair Francis
2023-06-14 1:19 ` [PULL 35/60] target/riscv: Reuse tb->flags.FS Alistair Francis
2023-06-14 1:19 ` [PULL 36/60] target/riscv: smstateen knobs Alistair Francis
2023-06-14 1:19 ` [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer Alistair Francis
2023-06-14 1:19 ` [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h Alistair Francis
2023-06-14 1:19 ` [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Alistair Francis
2023-06-14 1:19 ` [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions Alistair Francis
2023-06-14 1:19 ` [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions Alistair Francis
2023-06-14 1:19 ` [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Alistair Francis
2023-06-14 1:20 ` [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters Alistair Francis
2023-06-14 1:20 ` [PULL 44/60] disas/riscv.c: Remove redundant parentheses Alistair Francis
2023-06-14 1:20 ` [PULL 45/60] target/riscv: Fix target address to update badaddr Alistair Francis
2023-06-14 1:20 ` [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext Alistair Francis
2023-06-14 1:20 ` [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements Alistair Francis
2023-06-14 1:20 ` [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc Alistair Francis
2023-06-14 1:20 ` [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff Alistair Francis
2023-06-14 1:20 ` [PULL 50/60] target/riscv: Enable PC-relative translation Alistair Francis
2023-06-14 1:20 ` [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext Alistair Francis
2023-06-14 1:20 ` [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" Alistair Francis
2023-06-14 1:20 ` [PULL 53/60] riscv/virt: Support using pflash via -blockdev option Alistair Francis
2023-06-14 1:20 ` [PULL 54/60] docs/system: riscv: Add pflash usage details Alistair Francis
2023-06-14 1:20 ` [PULL 55/60] util/log: Add vector registers to log Alistair Francis
2023-06-14 1:20 ` [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask Alistair Francis
2023-06-14 1:20 ` [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE Alistair Francis
2023-06-14 1:20 ` [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements Alistair Francis
2023-06-14 1:20 ` [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP Alistair Francis
2023-06-14 1:20 ` [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Alistair Francis
2023-06-14 4:39 ` [PULL 00/60] riscv-to-apply queue Richard Henderson
2023-06-14 12:17 ` Michael Tokarev
2023-06-15 4:03 ` Alistair Francis [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAKmqyKPT9-Ru+AHhQR-N+2EctyWCdDY5nErT5Z0GbJ+zJfEcYw@mail.gmail.com \
--to=alistair23@gmail.com \
--cc=alistair.francis@wdc.com \
--cc=mjt@tls.msk.ru \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).