Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

From: Jonathan Behrens <jonathan@fintelia.io>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Alistair Francis <alistair23@gmail.com>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
Date: Tue, 21 Jan 2020 08:05:23 -0500	[thread overview]
Message-ID: <CANnJOVFZmmwvpdvLfr8r3VK1pudV_rmh3-iq_sgLZNsjkwQ_2A@mail.gmail.com> (raw)
In-Reply-To: <mhng-4545b3da-b9ba-4fa2-91e8-b0d7e66329d8@palmer-si-x1c4>

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I was just doubling checking the status of this patch because it conflicts
with the "RISC-V TIME CSR for privileged mode" PR that was just sent out,
and it seems this never got merged? In any case, perhaps these changes
should be rolled into that patch?

On Wed, Aug 21, 2019 at 1:37 PM Palmer Dabbelt <palmer@sifive.com> wrote:

> On Wed, 14 Aug 2019 20:19:39 PDT (-0700), jonathan@fintelia.io wrote:
> > Ping! What is the status of this patch?
>
> Sorry, I must have lost track of it.  I've added it to my patch queue.
>
> >
> > On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens <jonathan@fintelia.io>
> > wrote:
> >
> >> Bin, that proposal proved to be somewhat more controversial than I was
> >> expecting, since it was different than how currently available hardware
> >> worked. This option seemed much more likely to be accepted in the short
> >> term.
> >>
> >> Jonathan
> >>
> >> On Mon, Jul 1, 2019 at 9:26 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>
> >>> On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis <alistair23@gmail.com>
> >>> wrote:
> >>> >
> >>> > On Mon, Jul 1, 2019 at 8:56 AM <jonathan@fintelia.io> wrote:
> >>> > >
> >>> > > From: Jonathan Behrens <jonathan@fintelia.io>
> >>> > >
> >>> > > QEMU currently always triggers an illegal instruction exception
> when
> >>> > > code attempts to read the time CSR. This is valid behavor, but
> only if
> >>> > > the TM bit in mcounteren is hardwired to zero. This change also
> >>> > > corrects mcounteren and scounteren CSRs to be 32-bits on both
> 32-bit
> >>> > > and 64-bit targets.
> >>> > >
> >>> > > Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
> >>> >
> >>> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> >>> >
> >>>
> >>> I am a little bit lost here. I think we agreed to allow directly read
> >>> to time CSR when mcounteren.TM is set, no?
> >>>
> >>> Regards,
> >>> Bin
> >>>
> >>
>

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