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From: Alistair Francis <alistair@alistair23.me>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>
Subject: [Qemu-devel] [PATCH v3 2/6] target/arm: Allow setting M mode entry and sp
Date: Wed, 19 Jun 2019 04:54:00 +0000	[thread overview]
Message-ID: <PSXP216MB0277171F4F3978296BE895F2DDE50@PSXP216MB0277.KORP216.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <cover.1560919807.git.alistair@alistair23.me>

Add M mode initial entry PC and SP properties.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
---
 target/arm/cpu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h |  3 +++
 2 files changed, 50 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 376db154f0..1d83972ab1 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -301,6 +301,9 @@ static void arm_cpu_reset(CPUState *s)
              */
             initial_msp = ldl_p(rom);
             initial_pc = ldl_p(rom + 4);
+        } else if (cpu->init_sp || cpu->init_entry) {
+            initial_msp = cpu->init_sp;
+            initial_pc = cpu->init_entry;
         } else {
             /* Address zero not covered by a ROM blob, or the ROM blob
              * is in non-modifiable memory and this is a second reset after
@@ -801,6 +804,38 @@ static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
     visit_type_uint32(v, name, &cpu->init_svtor, errp);
 }
 
+static void arm_get_init_sp(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    visit_type_uint32(v, name, &cpu->init_sp, errp);
+}
+
+static void arm_set_init_sp(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    visit_type_uint32(v, name, &cpu->init_sp, errp);
+}
+
+static void arm_get_init_entry(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    visit_type_uint32(v, name, &cpu->init_entry, errp);
+}
+
+static void arm_set_init_entry(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    visit_type_uint32(v, name, &cpu->init_entry, errp);
+}
+
 void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -913,6 +948,18 @@ void arm_cpu_post_init(Object *obj)
         object_property_add(obj, "init-svtor", "uint32",
                             arm_get_init_svtor, arm_set_init_svtor,
                             NULL, NULL, &error_abort);
+    } else {
+        /*
+         * M profile: initial value of the SP and entry. We can't just use
+         * a simple DEFINE_PROP_UINT32 for this because we want to permit
+         * the property to be set after realize.
+         */
+        object_property_add(obj, "init-sp", "uint32",
+                            arm_get_init_sp, arm_set_init_sp,
+                            NULL, NULL, &error_abort);
+        object_property_add(obj, "init-entry", "uint32",
+                            arm_get_init_entry, arm_set_init_entry,
+                            NULL, NULL, &error_abort);
     }
 
     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f9da672be5..290fac19d3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -805,6 +805,9 @@ struct ARMCPU {
      */
     uint32_t psci_conduit;
 
+    /* For M, initial value of the entry and SP */
+    uint32_t init_sp, init_entry;
+
     /* For v8M, initial value of the Secure VTOR */
     uint32_t init_svtor;
 
-- 
2.11.0


  parent reply	other threads:[~2019-06-19  4:55 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <cover.1560919807.git.alistair@alistair23.me>
2019-06-19  4:53 ` [Qemu-devel] [PATCH v3 1/6] armv7m: Allow entry information to be returned Alistair Francis
2019-06-21 16:23   ` Philippe Mathieu-Daudé
2019-06-19  4:54 ` Alistair Francis [this message]
2019-06-21 16:38   ` [Qemu-devel] [PATCH v3 2/6] target/arm: Allow setting M mode entry and sp Philippe Mathieu-Daudé
2019-06-23 15:30     ` Alistair Francis
2019-06-19  4:54 ` [Qemu-devel] [PATCH v3 3/6] hw/misc: Add the STM32F4xx Sysconfig device Alistair Francis
2019-06-19  4:54 ` [Qemu-devel] [PATCH v3 4/6] hw/misc: Add the STM32F4xx EXTI device Alistair Francis
2019-06-19  4:54 ` [Qemu-devel] [PATCH v3 5/6] hw/arm: Add the STM32F4xx SoC Alistair Francis
2019-06-19  4:54 ` [Qemu-devel] [PATCH v3 6/6] hw/arm: Add the Netduino Plus 2 Alistair Francis

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