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From: Andrea Parri <andrea@rivosinc.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] riscv: Raise an exception if pte reserved bits are not cleared
Date: Mon, 17 Apr 2023 12:46:58 +0200	[thread overview]
Message-ID: <ZD0jos2r4uZocw/5@andrea> (raw)
In-Reply-To: <CAKmqyKNkyakGCFG0DqX02GpqhAPEq=tkt-EVctas5m2XjRuXJg@mail.gmail.com>

Hi Alistair,

> > @@ -936,6 +936,11 @@ restart:
> >              return TRANSLATE_FAIL;
> >          }
> >
> > +        /* PTE reserved bits must be cleared otherwise an exception is raised */
> > +        if (riscv_cpu_mxl(env) == MXL_RV64 && (pte & PTE_RESERVED)) {
> > +            return TRANSLATE_FAIL;
> > +        }
> 
> Isn't this caught by our existing check?
> 
>             if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
>                 return TRANSLATE_FAIL;
>             }

Thanks for checking this out.  AFAICS, the existing check/code doesn't
work if either svnapot or svpbmt are active.

Please let me know if you need other information.

  Andrea


  reply	other threads:[~2023-04-17 10:48 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-12  9:17 [PATCH] riscv: Raise an exception if pte reserved bits are not cleared Alexandre Ghiti
2023-04-17  3:24 ` Alistair Francis
2023-04-17 10:46   ` Andrea Parri [this message]
2023-04-18  2:22     ` Alistair Francis
2023-04-18  8:56       ` Alexandre Ghiti

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