From: "Wu, Fei" <fei2.wu@intel.com>
To: Bin Meng <bmeng@tinylab.org>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
"Palmer Dabbelt" <palmer@dabbelt.com>
Cc: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] target/riscv: Restore the predicate() NULL check behavior
Date: Wed, 12 Apr 2023 09:04:54 +0800 [thread overview]
Message-ID: <b0d06bc4-d8f1-30ff-9bc1-252c7f15df89@intel.com> (raw)
In-Reply-To: <20230411090211.3039186-1-bmeng@tinylab.org>
On 4/11/2023 5:02 PM, Bin Meng wrote:
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
I verified that 'csrr t3, 0x4' in user space didn't cause qemu exit but
raised illegal instruction after applying this patch.
Thanks,
Fei.
> This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
> Some comments are also added to indicate that predicate() must be
> provided for an implemented CSR.
>
> Reported-by: Fei Wu <fei2.wu@intel.com>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> target/riscv/csr.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d522efc0b6..736ab64275 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3797,6 +3797,11 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /* ensure CSR is implemented by checking predicate */
> + if (!csr_ops[csrno].predicate) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> /* privileged spec version check */
> if (env->priv_ver < csr_min_priv) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -3814,7 +3819,6 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> * illegal instruction exception should be triggered instead of virtual
> * instruction exception. Hence this comes after the read / write check.
> */
> - g_assert(csr_ops[csrno].predicate != NULL);
> RISCVException ret = csr_ops[csrno].predicate(env, csrno);
> if (ret != RISCV_EXCP_NONE) {
> return ret;
> @@ -3991,7 +3995,10 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
> return ret;
> }
>
> -/* Control and Status Register function table */
> +/*
> + * Control and Status Register function table
> + * riscv_csr_operations::predicate() must be provided for an implemented CSR
> + */
> riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> /* User Floating-Point CSRs */
> [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
next prev parent reply other threads:[~2023-04-12 1:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 9:02 [PATCH] target/riscv: Restore the predicate() NULL check behavior Bin Meng
2023-04-11 23:29 ` Daniel Henrique Barboza
2023-04-12 1:00 ` liweiwei
2023-04-12 1:04 ` Wu, Fei [this message]
2023-04-12 10:08 ` Philippe Mathieu-Daudé
2023-04-12 1:15 ` Alistair Francis
2023-04-12 1:32 ` LIU Zhiwei
2023-04-12 1:46 ` Alistair Francis
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