From: Jim Wilson <jimw@sifive.com>
To: Georg Kotheimer <georg.kotheimer@kernkonzept.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
Date: Fri, 23 Aug 2019 15:44:34 -0700 [thread overview]
Message-ID: <bee5ed64-7a65-c303-9cb6-8efcf4f8daf0@sifive.com> (raw)
In-Reply-To: <20190821162831.27811-1-georg.kotheimer@kernkonzept.com>
On 8/21/19 9:28 AM, Georg Kotheimer wrote:
> The size of the FPU registers depends solely on the floating point
> extensions supported by the target architecture.
> However, in the previous implementation the floating point register
> size was derived from whether the target architecture is 32-bit or
> 64-bit.
>
> To allow RVF without RVD, changes to riscv_gdb_get_fpu() and
> riscv_gdb_set_fpu() were necessary.
Reviewed-by: Jim Wilson <jimw@sifive.com>
Jim
next prev parent reply other threads:[~2019-08-23 22:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-21 16:28 [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions Georg Kotheimer
2019-08-23 22:44 ` Jim Wilson [this message]
2019-08-24 0:13 ` Alistair Francis
2020-01-07 11:26 ` Alex Bennée
2020-01-17 12:08 ` Alistair Francis
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