From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com,
alistair23@gmail.com
Subject: [PATCH v2 0/3] RISC-V: Populate mtval and stval
Date: Wed, 8 Sep 2021 14:54:13 +1000 [thread overview]
Message-ID: <cover.1631076834.git.alistair.francis@wdc.com> (raw)
From: Alistair Francis <alistair.francis@wdc.com>
Populate mtval and stval when taking an illegal instruction exception if
the features are set for the CPU.
Alistair Francis (3):
target/riscv: Set the opcode in DisasContext
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Set mtval and stval support
target/riscv/cpu.h | 6 +++++-
target/riscv/cpu.c | 6 +++++-
target/riscv/cpu_helper.c | 10 +++++++++
target/riscv/translate.c | 43 +++++++++++++++++++++------------------
4 files changed, 43 insertions(+), 22 deletions(-)
--
2.31.1
next reply other threads:[~2021-09-08 4:56 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-08 4:54 Alistair Francis [this message]
2021-09-08 4:54 ` [PATCH v2 1/3] target/riscv: Set the opcode in DisasContext Alistair Francis
2021-09-08 5:42 ` Bin Meng
2021-09-08 6:27 ` Richard Henderson
2021-09-08 4:54 ` [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
2021-09-08 5:53 ` Bin Meng
2021-09-08 6:48 ` Richard Henderson
2021-09-24 6:48 ` Alistair Francis
2021-09-24 12:57 ` Richard Henderson
2021-09-29 3:56 ` Alistair Francis
2021-09-08 4:54 ` [PATCH v2 3/3] target/riscv: Set mtval and stval support Alistair Francis
2021-09-08 5:55 ` Bin Meng
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