From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: peter.maydell@linaro.org, palmer@sifive.com,
alistair.francis@wdc.com, alistair23@gmail.com
Subject: [Qemu-devel] [PATCH v1 1/2] RISC-V: Handle bus errors in the page table walker
Date: Tue, 17 Sep 2019 16:22:59 -0700 [thread overview]
Message-ID: <dfb8bc9fb7cad494d53f89774a3a4a5f3e478792.1568762497.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1568762497.git.alistair.francis@wdc.com>
From: Palmer Dabbelt <palmer@sifive.com>
We directly access physical memory while walking the page tables on
RISC-V, but while doing so we were using cpu_ld*() which does not report
bus errors. This patch converts the page table walker over to use
address_space_ld*(), which allows bus errors to be detected.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6ece..c82e7ed52b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -169,7 +169,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
* (riscv_cpu_do_interrupt) is correct */
-
+ MemTxResult res;
+ MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmu_idx;
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
@@ -256,11 +257,16 @@ restart:
1 << MMU_DATA_LOAD, PRV_S)) {
return TRANSLATE_PMP_FAIL;
}
+
#if defined(TARGET_RISCV32)
- target_ulong pte = ldl_phys(cs->as, pte_addr);
+ target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
#elif defined(TARGET_RISCV64)
- target_ulong pte = ldq_phys(cs->as, pte_addr);
+ target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
#endif
+ if (res != MEMTX_OK) {
+ return TRANSLATE_FAIL;
+ }
+
hwaddr ppn = pte >> PTE_PPN_SHIFT;
if (!(pte & PTE_V)) {
--
2.23.0
next prev parent reply other threads:[~2019-09-17 23:31 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-17 23:22 [Qemu-devel] [PATCH v1 0/2] RISC-V: Convert to do_transaction_failed hook Alistair Francis
2019-09-17 23:22 ` Alistair Francis [this message]
2019-09-21 9:09 ` [Qemu-devel] [PATCH v1 1/2] RISC-V: Handle bus errors in the page table walker Philippe Mathieu-Daudé
2019-09-17 23:23 ` [Qemu-devel] [PATCH v1 2/2] RISC-V: Implement cpu_do_transaction_failed Alistair Francis
2019-09-21 9:07 ` Philippe Mathieu-Daudé
2019-09-18 2:15 ` [Qemu-devel] [PATCH v1 0/2] RISC-V: Convert to do_transaction_failed hook Richard Henderson
2019-09-20 22:48 ` Palmer Dabbelt
2019-09-23 17:53 ` Alistair Francis
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