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Tue, 10 Sep 2019 07:48:05 -0700 (PDT) Date: Tue, 10 Sep 2019 07:48:05 -0700 (PDT) X-Google-Original-Date: Tue, 10 Sep 2019 07:42:56 PDT (-0700) In-Reply-To: From: Palmer Dabbelt To: Alistair Francis Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.68 Subject: Re: [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , qemu-devel@nongnu.org, Atish Patra , Alistair Francis , alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 23 Aug 2019 16:38:02 PDT (-0700), Alistair Francis wrote: > As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip > is 32-bit as well. > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.h | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3a95c41428..4c342e7a79 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -154,6 +154,23 @@ struct CPURISCVState { > target_ulong mcause; > target_ulong mtval; /* since: priv-1.10.0 */ > > + /* Hypervisor CSRs */ > + target_ulong hstatus; > + target_ulong hedeleg; > + target_ulong hideleg; > + target_ulong hgatp; > + > + /* Virtual CSRs */ > + target_ulong vsstatus; > + uint32_t vsip; > + target_ulong vsie; > + target_ulong vstvec; > + target_ulong vsscratch; > + target_ulong vsepc; > + target_ulong vscause; > + target_ulong vstval; > + target_ulong vsatp; > + > target_ulong scounteren; > target_ulong mcounteren; Reviewed-by: Palmer Dabbelt