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From: Palmer Dabbelt <palmer@sifive.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	alistair23@gmail.com
Subject: Re: [Qemu-devel] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR
Date: Mon, 24 Jun 2019 02:31:41 -0700 (PDT)	[thread overview]
Message-ID: <mhng-e848dd5f-d245-421a-aafc-857a10800e30@palmer-si-x1e> (raw)
In-Reply-To: <b9cb270c4356301ca15d6fec3f651da64beb57d3.1560821342.git.alistair.francis@wdc.com>

On Mon, 17 Jun 2019 18:31:08 PDT (-0700), Alistair Francis wrote:
> Add a comment for the new mcountinhibit which conflicts with the
> CSR_MUCOUNTEREN from version 1.09.1. This can be updated when we remove
> 1.09.1.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 6 ++++--
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 47450a3cdb..11f971ad5d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -136,6 +136,7 @@
>  #define CSR_MCOUNTEREN      0x306
>
>  /* Legacy Counter Setup (priv v1.9.1) */
> +/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
>  #define CSR_MUCOUNTEREN     0x320
>  #define CSR_MSCOUNTEREN     0x321
>  #define CSR_MHCOUNTEREN     0x322
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c67d29e206..437387fd28 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -461,18 +461,20 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
>      return 0;
>  }
>
> +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
>  {
> -    if (env->priv_ver > PRIV_VERSION_1_09_1) {
> +    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
>          return -1;
>      }
>      *val = env->mcounteren;
>      return 0;
>  }
>
> +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
>  {
> -    if (env->priv_ver > PRIV_VERSION_1_09_1) {
> +    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
>          return -1;
>      }
>      env->mcounteren = val;

I don't think this one is right: this should be unsupported on 1.11, as the
semantics of this bit are slightly different.  It shouldn't be that hard to
just emulate it fully for both 1.09.1 and 1.11: for 1.09 this disables access
to the counters (which still tick), while for 1.11 it disables ticking the
counters (which can still be accessed).  Since we don't do anything with the
counters in QEMU, I think this should do it

LMK if you're OK with me replacing the patch with this

commit e9169ccd5ca97a036de41dad23f37f6724712b90
Author: Alistair Francis <alistair.francis@wdc.com>
Date:   Mon Jun 17 18:31:08 2019 -0700

    target/riscv: Add the mcountinhibit CSR

    1.11 defines mcountinhibit, which has the same numeric CSR value as
    mucounteren from 1.09.1 but has different semantics.  This patch enables
    the CSR for 1.11-based targets, which is trivial to implement because
    the counters in QEMU never tick (legal according to the spec).

    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
    [Palmer: Fix counter access semantics, change commit message to indicate
    the behavior is fully emulated.]
    Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
    Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 47450a3cdb75..11f971ad5df0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -136,6 +136,7 @@
 #define CSR_MCOUNTEREN      0x306

 /* Legacy Counter Setup (priv v1.9.1) */
+/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
 #define CSR_MUCOUNTEREN     0x320
 #define CSR_MSCOUNTEREN     0x321
 #define CSR_MHCOUNTEREN     0x322
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c67d29e20618..2622b2e05474 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,6 +56,14 @@ static int fs(CPURISCVState *env, int csrno)
 static int ctr(CPURISCVState *env, int csrno)
 {
 #if !defined(CONFIG_USER_ONLY)
+    /*
+     * The counters are always enabled on newer priv specs, as the CSR has
+     * changed from controlling that the counters can be read to controlling
+     * that the counters increment.
+     */
+    if (env->priv_ver > PRIV_VERSION_1_09_1)
+        return 0;
+
     uint32_t ctr_en = ~0u;

     if (env->priv < PRV_M) {
@@ -461,18 +469,20 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }

+/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 {
-    if (env->priv_ver > PRIV_VERSION_1_09_1) {
+    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
         return -1;
     }
     *val = env->mcounteren;
     return 0;
 }

+/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 {
-    if (env->priv_ver > PRIV_VERSION_1_09_1) {
+    if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver < PRIV_VERSION_1_11_0) {
         return -1;
     }
     env->mcounteren = val;


  reply	other threads:[~2019-06-24  9:34 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-18  1:31 [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs Alistair Francis
2019-06-18  5:23   ` Philippe Mathieu-Daudé
2019-06-18 15:59     ` Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 2/9] target/riscv: Add the privledge spec version 1.11.0 Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR Alistair Francis
2019-06-24  9:31   ` Palmer Dabbelt [this message]
2019-06-24 20:14     ` Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 4/9] target/riscv: Set privledge spec 1.11.0 as default Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 5/9] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 6/9] target/riscv: Require either I or E base extension Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 7/9] target/riscv: Remove user version information Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 8/9] target/riscv: Add support for disabling/enabling Counters Alistair Francis
2019-06-18  1:31 ` [Qemu-devel] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options Alistair Francis
2019-06-24  9:31   ` Palmer Dabbelt
2019-06-24 23:16     ` Alistair Francis
2019-06-25 10:08       ` Palmer Dabbelt
2019-06-19 10:58 ` [Qemu-devel] [PATCH v1 0/9] Update the RISC-V specification versions Palmer Dabbelt
2019-06-19 14:19   ` Alistair Francis
2019-06-21  2:49     ` Palmer Dabbelt
2019-06-22  0:23       ` Alistair Francis
2019-06-23 14:40         ` Palmer Dabbelt
2019-06-24  9:33 ` Palmer Dabbelt
2019-06-24 20:13   ` Alistair Francis

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