Re: Questions about CXL device (type 3 memory) hotplug

From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Vikram Sethi <vsethi@nvidia.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
	"Yasunori Gotou (Fujitsu)" <y-goto@fujitsu.com>,
	"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
	"catalin.marinas@arm.com" <Catalin.Marinas@arm.com>,
	James Morse <james.morse@arm.com>,
	"Natu, Mahesh" <mahesh.natu@intel.com>
Subject: Re: Questions about CXL device (type 3 memory) hotplug
Date: Thu, 8 Jun 2023 11:41:17 -0700	[thread overview]
Message-ID: <648220cdade2_1433ac2949b@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20230608161911.00000912@Huawei.com>

Jonathan Cameron wrote:
> On Wed, 7 Jun 2023 18:44:36 +0000
> Vikram Sethi <vsethi@nvidia.com> wrote:
[..]
> > > So flush before to make clean (or invalid but then potentially
> > > prefetched so clean) - tear down the HDM decoders and flush again /
> > > invalidate so nothing stale hanging around (or do it before
> > > bringing something new up at that Host PA). Eat or log any errors
> > > and don't worry about it. 
> > 
> > I'm OK with this approach. When the cache flush is done at the time
> > of the decoder tear down, there mustn't be any page table mappings to
> > the decode HPA ranges (and if any ISA wanted to do an in kernel flush
> > vs FW call, and needed a PTE mapping for the flush, that should be
> > done with a non cacheable mapping).
> 
> FW magic so we don't have to care :)

Hopefully a pre-HDM-teardown flush for draining writebacks and
pre-HDM-setup-flush for clearing out clean lines brought in by
speculation is sufficient. My worry with "FW magic" is that when it
breaks the phone rings for kernel help.