From: Marc Zyngier <maz@kernel.org>
To: Ehsan Aghapour <aghapour.ehsan17@gmail.com>
Cc: linux-amlogic@lists.infradead.org, mark.rutland@arm.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: Enable "PMU" counters for Khadas VIM3 in the Google AOSP kernel
Date: Fri, 08 Oct 2021 09:21:47 +0100 [thread overview]
Message-ID: <8735pcq63o.wl-maz@kernel.org> (raw)
In-Reply-To: <CAHjmVnpUof2Nvbuuw6uQ31w5LNoCrYjV0Z+Eya0FLiQ29drKmA@mail.gmail.com>
On Thu, 07 Oct 2021 23:13:30 +0100,
Ehsan Aghapour <aghapour.ehsan17@gmail.com> wrote:
>
> I am working on Google AOSP kernel and require to enable PMU. PMU is
> working well in Khadas kernel for both A53 and A73 cores but it is not
> enabled in Google AOSP kernel 5.4. I try adding arm_pmu definition in
> device tree at /arch/arm64/boot/dts/amlogic/meson-g12b.dtsi as follow:
> arm_pmu {
> compatible = "arm,armv8-pmuv3";
> clusterb-enabled;
> interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff634680 0x0 0x4>,
> <0x0 0xff6347c0 0x0 0x04>;
> cpumasks = <0x3 0x3C>;
> /* default 10ms */
> relax-timer-ns = <10000000>;
> /* default 10000us */
> max-wait-cnt = <10000>;
Most of these properties don't exist in the binding, and are thus
ignored by the driver.
> };
>
> However in this case I only see A53 performance counters in DS5 Streamline
> and performance counters of A73 cores are zero yet.
>
> Would you please help me solve the problem? (If device tree need change or
> kernel config to enable pmu counters for both CPUs).
The problem is that all the Amlogic SoCs have a totally broken PMU
integration. They OR'd all the PMU interrupts from the CPUs inside a
cluster, which is why you end-up with only two interrupts in a system
that should have 6.
There is no good workaround for this. The downstream kernel may have
all sort of hacks to cope with the brokenness, but upstream will
simply not work. I have my own set of hacks to deal with the PMU on
the A55-based version of that SoC[1], but there is no way this is
going upstream.
Thanks,
M.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/commit/?h=hack/vim3l-crap&id=6bde69695241344ddf7f74880314a0c6cbdaf963
--
Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Ehsan Aghapour <aghapour.ehsan17@gmail.com>
Cc: linux-amlogic@lists.infradead.org, mark.rutland@arm.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: Enable "PMU" counters for Khadas VIM3 in the Google AOSP kernel
Date: Fri, 08 Oct 2021 09:21:47 +0100 [thread overview]
Message-ID: <8735pcq63o.wl-maz@kernel.org> (raw)
In-Reply-To: <CAHjmVnpUof2Nvbuuw6uQ31w5LNoCrYjV0Z+Eya0FLiQ29drKmA@mail.gmail.com>
On Thu, 07 Oct 2021 23:13:30 +0100,
Ehsan Aghapour <aghapour.ehsan17@gmail.com> wrote:
>
> I am working on Google AOSP kernel and require to enable PMU. PMU is
> working well in Khadas kernel for both A53 and A73 cores but it is not
> enabled in Google AOSP kernel 5.4. I try adding arm_pmu definition in
> device tree at /arch/arm64/boot/dts/amlogic/meson-g12b.dtsi as follow:
> arm_pmu {
> compatible = "arm,armv8-pmuv3";
> clusterb-enabled;
> interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff634680 0x0 0x4>,
> <0x0 0xff6347c0 0x0 0x04>;
> cpumasks = <0x3 0x3C>;
> /* default 10ms */
> relax-timer-ns = <10000000>;
> /* default 10000us */
> max-wait-cnt = <10000>;
Most of these properties don't exist in the binding, and are thus
ignored by the driver.
> };
>
> However in this case I only see A53 performance counters in DS5 Streamline
> and performance counters of A73 cores are zero yet.
>
> Would you please help me solve the problem? (If device tree need change or
> kernel config to enable pmu counters for both CPUs).
The problem is that all the Amlogic SoCs have a totally broken PMU
integration. They OR'd all the PMU interrupts from the CPUs inside a
cluster, which is why you end-up with only two interrupts in a system
that should have 6.
There is no good workaround for this. The downstream kernel may have
all sort of hacks to cope with the brokenness, but upstream will
simply not work. I have my own set of hacks to deal with the PMU on
the A55-based version of that SoC[1], but there is no way this is
going upstream.
Thanks,
M.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/commit/?h=hack/vim3l-crap&id=6bde69695241344ddf7f74880314a0c6cbdaf963
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Ehsan Aghapour <aghapour.ehsan17@gmail.com>
Cc: linux-amlogic@lists.infradead.org, mark.rutland@arm.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: Enable "PMU" counters for Khadas VIM3 in the Google AOSP kernel
Date: Fri, 08 Oct 2021 09:21:47 +0100 [thread overview]
Message-ID: <8735pcq63o.wl-maz@kernel.org> (raw)
In-Reply-To: <CAHjmVnpUof2Nvbuuw6uQ31w5LNoCrYjV0Z+Eya0FLiQ29drKmA@mail.gmail.com>
On Thu, 07 Oct 2021 23:13:30 +0100,
Ehsan Aghapour <aghapour.ehsan17@gmail.com> wrote:
>
> I am working on Google AOSP kernel and require to enable PMU. PMU is
> working well in Khadas kernel for both A53 and A73 cores but it is not
> enabled in Google AOSP kernel 5.4. I try adding arm_pmu definition in
> device tree at /arch/arm64/boot/dts/amlogic/meson-g12b.dtsi as follow:
> arm_pmu {
> compatible = "arm,armv8-pmuv3";
> clusterb-enabled;
> interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff634680 0x0 0x4>,
> <0x0 0xff6347c0 0x0 0x04>;
> cpumasks = <0x3 0x3C>;
> /* default 10ms */
> relax-timer-ns = <10000000>;
> /* default 10000us */
> max-wait-cnt = <10000>;
Most of these properties don't exist in the binding, and are thus
ignored by the driver.
> };
>
> However in this case I only see A53 performance counters in DS5 Streamline
> and performance counters of A73 cores are zero yet.
>
> Would you please help me solve the problem? (If device tree need change or
> kernel config to enable pmu counters for both CPUs).
The problem is that all the Amlogic SoCs have a totally broken PMU
integration. They OR'd all the PMU interrupts from the CPUs inside a
cluster, which is why you end-up with only two interrupts in a system
that should have 6.
There is no good workaround for this. The downstream kernel may have
all sort of hacks to cope with the brokenness, but upstream will
simply not work. I have my own set of hacks to deal with the PMU on
the A55-based version of that SoC[1], but there is no way this is
going upstream.
Thanks,
M.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/commit/?h=hack/vim3l-crap&id=6bde69695241344ddf7f74880314a0c6cbdaf963
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next parent reply other threads:[~2021-10-08 8:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAHjmVnpUof2Nvbuuw6uQ31w5LNoCrYjV0Z+Eya0FLiQ29drKmA@mail.gmail.com>
2021-10-08 8:21 ` Marc Zyngier [this message]
2021-10-08 8:21 ` Enable "PMU" counters for Khadas VIM3 in the Google AOSP kernel Marc Zyngier
2021-10-08 8:21 ` Marc Zyngier
2021-10-07 23:11 Ehsan Aghapour
2021-10-07 23:11 ` Ehsan Aghapour
2021-10-07 23:11 ` Ehsan Aghapour
2021-10-14 10:53 ` Robin Murphy
2021-10-14 10:53 ` Robin Murphy
2021-10-14 10:53 ` Robin Murphy
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