From: James Morse <james.morse@arm.com>
To: stable@vger.kernel.org
Cc: catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org,
james.morse@arm.com
Subject: [stable:PATCH v5.4.184 04/22] arm64: Add Cortex-X2 CPU part definition
Date: Tue, 15 Mar 2022 18:23:57 +0000 [thread overview]
Message-ID: <20220315182415.3900464-5-james.morse@arm.com> (raw)
In-Reply-To: <20220315182415.3900464-1-james.morse@arm.com>
From: Anshuman Khandual <anshuman.khandual@arm.com>
commit 72bb9dcb6c33cfac80282713c2b4f2b254cd24d1 upstream.
Add the CPU Partnumbers for the new Arm designs.
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1642994138-25887-2-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 6a0acbec77ae..e4394be47d35 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -73,6 +73,7 @@
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
#define ARM_CPU_PART_CORTEX_A77 0xD0D
#define ARM_CPU_PART_CORTEX_A710 0xD47
+#define ARM_CPU_PART_CORTEX_X2 0xD48
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define APM_CPU_PART_POTENZA 0x000
@@ -107,6 +108,7 @@
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
+#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
--
2.30.2
next prev parent reply other threads:[~2022-03-15 18:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-15 18:23 [stable:PATCH v5.4.184 00/22] arm64: Mitigate spectre style branch history side channels James Morse
2022-03-15 18:23 ` [stable:PATCH v5.4.184 01/22] arm64: Add part number for Arm Cortex-A77 James Morse
2022-03-15 18:23 ` [stable:PATCH v5.4.184 02/22] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition James Morse
2022-03-15 18:23 ` [stable:PATCH v5.4.184 03/22] arm64: add ID_AA64ISAR2_EL1 sys register James Morse
2022-03-15 18:23 ` James Morse [this message]
2022-03-15 18:23 ` [stable:PATCH v5.4.184 05/22] arm64: entry.S: Add ventry overflow sanity checks James Morse
2022-03-15 18:23 ` [stable:PATCH v5.4.184 06/22] arm64: entry: Make the trampoline cleanup optional James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 07/22] arm64: entry: Free up another register on kpti's tramp_exit path James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 08/22] arm64: entry: Move the trampoline data page before the text page James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 09/22] arm64: entry: Allow tramp_alias to access symbols after the 4K boundary James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 10/22] arm64: entry: Don't assume tramp_vectors is the start of the vectors James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 11/22] arm64: entry: Move trampoline macros out of ifdef'd section James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 12/22] arm64: entry: Make the kpti trampoline's kpti sequence optional James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 13/22] arm64: entry: Allow the trampoline text to occupy multiple pages James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 14/22] arm64: entry: Add non-kpti __bp_harden_el1_vectors for mitigations James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 15/22] arm64: entry: Add vectors that have the bhb mitigation sequences James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 16/22] arm64: entry: Add macro for reading symbol addresses from the trampoline James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 17/22] arm64: Add percpu vectors for EL1 James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 18/22] arm64: proton-pack: Report Spectre-BHB vulnerabilities as part of Spectre-v2 James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 19/22] KVM: arm64: Add templates for BHB mitigation sequences James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 20/22] arm64: Mitigate spectre style branch history side channels James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 21/22] KVM: arm64: Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migrated James Morse
2022-03-15 18:24 ` [stable:PATCH v5.4.184 22/22] arm64: Use the clearbhb instruction in mitigations James Morse
2022-03-16 15:41 ` [stable:PATCH v5.4.184 00/22] arm64: Mitigate spectre style branch history side channels Sasha Levin
2022-03-16 17:38 ` James Morse
2022-03-16 18:43 ` Sasha Levin
2022-03-17 10:00 ` Greg KH
2022-03-18 12:15 ` James Morse
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220315182415.3900464-5-james.morse@arm.com \
--to=james.morse@arm.com \
--cc=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=stable@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).