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From: Bin Meng <bmeng@tinylab.org>
To: u-boot@lists.denx.de
Cc: "Anup Patel" <anup@brainfault.org>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Atish Patra" <atishp@atishpatra.org>,
	"Bin Meng" <bmeng.cn@gmail.com>,
	"Kautuk Consul" <kconsul@ventanamicro.com>,
	Leo <ycliang@andestech.com>, "Michael Walle" <michael@walle.cc>,
	"Michal Simek" <michal.simek@amd.com>,
	"Nikita Shubin" <n.shubin@yadro.com>,
	"Pali Rohár" <pali@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Rick Chen" <rick@andestech.com>,
	"Sean Anderson" <seanga2@gmail.com>,
	"Sergei Antonov" <saproj@gmail.com>,
	"Svyatoslav Ryhel" <clamor95@gmail.com>,
	"Tianrui Wei" <tianrui-wei@outlook.com>, Tom <twarren@nvidia.com>,
	"William Zhang" <william.zhang@broadcom.com>,
	"Yanhong Wang" <yanhong.wang@starfivetech.com>,
	"Yu Chien Peter Lin" <peterlin@andestech.com>
Subject: [PATCH v2 0/3] riscv: Add ACLINT mtimer and mswi devices support
Date: Wed, 21 Jun 2023 23:11:43 +0800	[thread overview]
Message-ID: <20230621151147.1523273-1-bmeng@tinylab.org> (raw)

This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.

This seriesl updates U-Boot existing SiFive CLINT driver to handle
the ACLINT changes, and is now able to support both CLINT and ACLINT.

With this series, U-Boot is able to boot on:

- QEMU 'virt' machine with 'aclint=on'
- Rocket Chip with ACLINT changes [2]

[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
[2] https://github.com/chipsalliance/rocket-chip/pull/3330

Changes in v2:
- drop ae350.h changes

Bin Meng (3):
  riscv: timer: Update the sifive clint timer driver to support aclint
  riscv: clint: Update the sifive clint ipi driver to support aclint
  riscv: Rename SiFive CLINT to RISC-V ALINT

 MAINTAINERS                                   |  2 +-
 arch/riscv/Kconfig                            | 12 ++-
 arch/riscv/cpu/fu540/Kconfig                  |  2 +-
 arch/riscv/cpu/fu740/Kconfig                  |  2 +-
 arch/riscv/cpu/generic/Kconfig                |  4 +-
 arch/riscv/cpu/jh7110/Kconfig                 |  2 +-
 arch/riscv/include/asm/global_data.h          |  4 +-
 arch/riscv/include/asm/syscon.h               |  2 +-
 arch/riscv/lib/Makefile                       |  2 +-
 .../lib/{sifive_clint.c => aclint_ipi.c}      | 31 ++++++--
 board/openpiton/riscv64/Kconfig               |  2 +-
 board/sipeed/maix/Kconfig                     |  2 +-
 drivers/timer/Makefile                        |  2 +-
 drivers/timer/riscv_aclint_timer.c            | 74 +++++++++++++++++++
 drivers/timer/sifive_clint_timer.c            | 68 -----------------
 include/configs/qemu-riscv.h                  |  2 +-
 include/configs/sifive-unleashed.h            |  2 +-
 include/configs/starfive-visionfive2.h        |  1 +
 18 files changed, 123 insertions(+), 93 deletions(-)
 rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (53%)
 create mode 100644 drivers/timer/riscv_aclint_timer.c
 delete mode 100644 drivers/timer/sifive_clint_timer.c

-- 
2.25.1


             reply	other threads:[~2023-06-21 15:13 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-21 15:11 Bin Meng [this message]
2023-06-21 15:11 ` [PATCH v2 1/3] riscv: timer: Update the sifive clint timer driver to support aclint Bin Meng
     [not found]   ` <SEZPR03MB806458A90D2E7EEE6C96C947C126A@SEZPR03MB8064.apcprd03.prod.outlook.com>
2023-06-26  2:11     ` Rick Chen
2023-06-21 15:11 ` [PATCH v2 2/3] riscv: clint: Update the sifive clint ipi " Bin Meng
2023-06-21 15:11 ` [PATCH v2 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT Bin Meng
2023-06-24  9:12   ` Pali Rohár

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