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Thu, 6 Jul 2023 12:46:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 366AjxrS056438; Thu, 6 Jul 2023 18:45:59 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 6 Jul 2023 18:45:55 +0800 Date: Thu, 6 Jul 2023 10:45:51 +0000 From: Leo Liang To: CC: , Subject: [PULL] u-boot-riscv/riscv-for-next Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 366AjxrS056438 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi Tom, The following changes since commit e80f4079b3a3db0961b73fa7a96e6c90242d8d25: Merge tag 'v2023.07-rc6' into next (2023-07-05 11:28:55 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git riscv-for-next for you to fetch changes up to 12f66e2197c59e500d1e2ee359bb2ce22d748290: board: ae350: Add missing env variables for booti (2023-07-06 17:28:08 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/16799 ---------------------------------------------------------------- - RISC-V CI OpenSBI version update - Andes ae350 board modification - Sync PolarFire SoC dts with Linux - Support building ubifs ---------------------------------------------------------------- Ben Dooks (4): riscv: add generic link for riscv: implement local_irq_{save,restore} macros riscv: define test_and_{set,clear}_bit in asm/bitops.h clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCI Bin Meng (1): ci: riscv: Update OpenSBI to v1.2 Conor Dooley (3): riscv: dts: drop microchip from dts filenames riscv: dts: sync mpfs-icicle devicetree with linux board: microchip: set mac address for ethernet1 on icicle Heinrich Schuchardt (2): cmd/sbi: display new extensions RISC-V: CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS description Hoegeun Kwon (1): clk: starfive: pll: Fix to use postdiv1_mask Yu Chien Peter Lin (2): riscv: andes_plicsw: Fix IPI during OpenSBI invocation board: ae350: Add missing env variables for booti .azure-pipelines.yml | 8 +-- .gitlab-ci.yml | 8 +-- arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 136 ------------------------------------------- arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi | 71 +++++++++++++++++++++++ arch/riscv/dts/{microchip-mpfs-icicle-kit-u-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} | 0 arch/riscv/dts/mpfs-icicle-kit.dts | 208 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} | 434 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------------------------------------------------ arch/riscv/include/asm/atomic.h | 14 +++++ arch/riscv/include/asm/bitops.h | 3 + arch/riscv/include/asm/sbi.h | 9 +++ arch/riscv/include/asm/system.h | 17 ++++-- arch/riscv/lib/andes_plicsw.c | 25 +++++++- board/microchip/mpfs_icicle/mpfs_icicle.c | 15 ++++- cmd/riscv/sbi.c | 3 + common/spl/Kconfig | 6 +- configs/microchip_mpfs_icicle_defconfig | 2 +- doc/board/microchip/mpfs_icicle.rst | 6 +- drivers/clk/sifive/Makefile | 4 +- drivers/clk/starfive/clk-jh7110-pll.c | 2 +- include/configs/ae350.h | 14 +++-- include/dt-bindings/clock/microchip-mpfs-clock.h | 29 +++++++++- include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h | 196 -------------------------------------------------------------- include/dt-bindings/interrupt-controller/riscv-hart.h | 17 ------ 24 files changed, 597 insertions(+), 632 deletions(-) delete mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi rename arch/riscv/dts/{microchip-mpfs-icicle-kit-u-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} (100%) create mode 100644 arch/riscv/dts/mpfs-icicle-kit.dts rename arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} (57%) create mode 100644 arch/riscv/include/asm/atomic.h delete mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h delete mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h Best regards, Leo