From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 2/3] x86emul: check host features alongside guest ones where needed Date: Fri, 11 Mar 2016 10:34:28 -0700 Message-ID: <56E30FB402000078000DBB8F@prv-mh.provo.novell.com> References: <56E30EA102000078000DBB7F@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part685FD0B4.1__=" Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aeQxK-0004FO-EY for xen-devel@lists.xenproject.org; Fri, 11 Mar 2016 17:34:30 +0000 In-Reply-To: <56E30EA102000078000DBB7F@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper , Keir Fraser List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part685FD0B4.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1093,6 +1093,22 @@ static bool_t vcpu_has( #define vcpu_must_have_cx16() vcpu_must_have(0x00000001, ECX, 13) #define vcpu_must_have_avx() vcpu_must_have(0x00000001, ECX, 28) =20 +#ifdef __XEN__ +/* + * Note the (subtle?) difference between vcpu_must_have_() and + * vcpu_must_have(): The former only checks guest feature flags, + * while the latter also checks host ones, i.e. is required to be used = when + * emulation code is using the same instruction class for carrying out = the + * actual operation). + */ +#define host_and_vcpu_must_have(feat) ({ \ + generate_exception_if(!cpu_has_##feat, EXC_UD, -1); \ + vcpu_must_have_##feat(); \ +}) +#else +#define host_and_vcpu_must_have(feat) vcpu_must_have_##feat() +#endif + static int in_longmode( struct x86_emulate_ctxt *ctxt, @@ -3102,7 +3118,7 @@ x86_emulate( emulate_fpu_insn_memsrc("fildl", src.val); break; case 1: /* fisttp m32i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes =3D 4; dst =3D ea; dst.type =3D OP_MEM; @@ -3211,7 +3227,7 @@ x86_emulate( emulate_fpu_insn_memsrc("fldl", src.val); break; case 1: /* fisttp m64i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes =3D 8; dst =3D ea; dst.type =3D OP_MEM; @@ -3319,7 +3335,7 @@ x86_emulate( emulate_fpu_insn_memsrc("filds", src.val); break; case 1: /* fisttp m16i */ - vcpu_must_have_sse3(); + host_and_vcpu_must_have(sse3); ea.bytes =3D 2; dst =3D ea; dst.type =3D OP_MEM; @@ -4115,9 +4131,9 @@ x86_emulate( if ( vex.opcx =3D=3D vex_none ) { if ( vex.pfx & VEX_PREFIX_DOUBLE_MASK ) - vcpu_must_have_sse2(); + host_and_vcpu_must_have(sse2); else - vcpu_must_have_sse(); + host_and_vcpu_must_have(sse); ea.bytes =3D 16; SET_SSE_PREFIX(buf[0], vex.pfx); get_fpu(X86EMUL_FPU_xmm, &fic); @@ -4128,7 +4144,7 @@ x86_emulate( ((vex.reg !=3D 0xf) && ((ea.type =3D=3D OP_MEM) || !(vex.pfx & VEX_PREFIX_SCALAR_MASK)))); - vcpu_must_have_avx(); + host_and_vcpu_must_have(avx); get_fpu(X86EMUL_FPU_ymm, &fic); ea.bytes =3D 16 << vex.l; } @@ -4361,16 +4377,16 @@ x86_emulate( { case vex_66: case vex_f3: - vcpu_must_have_sse2(); + host_and_vcpu_must_have(sse2); buf[0] =3D 0x66; /* movdqa */ get_fpu(X86EMUL_FPU_xmm, &fic); ea.bytes =3D 16; break; case vex_none: if ( b !=3D 0xe7 ) - vcpu_must_have_mmx(); + host_and_vcpu_must_have(mmx); else - vcpu_must_have_sse(); + host_and_vcpu_must_have(sse); get_fpu(X86EMUL_FPU_mmx, &fic); ea.bytes =3D 8; break; @@ -4382,7 +4398,7 @@ x86_emulate( { fail_if((vex.opcx !=3D vex_0f) || (vex.reg !=3D 0xf) || ((vex.pfx !=3D vex_66) && (vex.pfx !=3D vex_f3))); - vcpu_must_have_avx(); + host_and_vcpu_must_have(avx); get_fpu(X86EMUL_FPU_ymm, &fic); ea.bytes =3D 16 << vex.l; } @@ -4688,7 +4704,7 @@ x86_emulate( generate_exception_if((modrm_reg & 7) !=3D 1, EXC_UD, -1); generate_exception_if(ea.type !=3D OP_MEM, EXC_UD, -1); if ( op_bytes =3D=3D 8 ) - vcpu_must_have_cx16(); + host_and_vcpu_must_have(cx16); op_bytes *=3D 2; =20 /* Get actual old value. */ --=__Part685FD0B4.1__= Content-Type: text/plain; name="x86emul-host-features.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86emul-host-features.patch" x86emul: check host features alongside guest ones where needed=0A=0ASigned-= off-by: Jan Beulich =0A=0A--- a/xen/arch/x86/x86_emulate= /x86_emulate.c=0A+++ b/xen/arch/x86/x86_emulate/x86_emulate.c=0A@@ -1093,6 = +1093,22 @@ static bool_t vcpu_has(=0A #define vcpu_must_have_cx16() = vcpu_must_have(0x00000001, ECX, 13)=0A #define vcpu_must_have_avx() = vcpu_must_have(0x00000001, ECX, 28)=0A =0A+#ifdef __XEN__=0A+/*=0A+ * Note = the (subtle?) difference between vcpu_must_have_() and=0A+ * = vcpu_must_have(): The former only checks guest feature flags,=0A+ = * while the latter also checks host ones, i.e. is required to be used = when=0A+ * emulation code is using the same instruction class for carrying = out the=0A+ * actual operation).=0A+ */=0A+#define host_and_vcpu_must_have(= feat) ({ \=0A+ generate_exception_if(!cpu_has_##feat, EXC_UD, -1); = \=0A+ vcpu_must_have_##feat(); \=0A+})=0A+#else=0A+#define host_and_vcpu= _must_have(feat) vcpu_must_have_##feat()=0A+#endif=0A+=0A static int=0A = in_longmode(=0A struct x86_emulate_ctxt *ctxt,=0A@@ -3102,7 +3118,7 @@ = x86_emulate(=0A emulate_fpu_insn_memsrc("fildl", = src.val);=0A break;=0A case 1: /* fisttp m32i = */=0A- vcpu_must_have_sse3();=0A+ host_and_vc= pu_must_have(sse3);=0A ea.bytes =3D 4;=0A = dst =3D ea;=0A dst.type =3D OP_MEM;=0A@@ -3211,7 +3227,7 = @@ x86_emulate(=0A emulate_fpu_insn_memsrc("fldl", = src.val);=0A break;=0A case 1: /* fisttp m64i = */=0A- vcpu_must_have_sse3();=0A+ host_and_vc= pu_must_have(sse3);=0A ea.bytes =3D 8;=0A = dst =3D ea;=0A dst.type =3D OP_MEM;=0A@@ -3319,7 +3335,7 = @@ x86_emulate(=0A emulate_fpu_insn_memsrc("filds", = src.val);=0A break;=0A case 1: /* fisttp m16i = */=0A- vcpu_must_have_sse3();=0A+ host_and_vc= pu_must_have(sse3);=0A ea.bytes =3D 2;=0A = dst =3D ea;=0A dst.type =3D OP_MEM;=0A@@ -4115,9 +4131,9 = @@ x86_emulate(=0A if ( vex.opcx =3D=3D vex_none )=0A {=0A = if ( vex.pfx & VEX_PREFIX_DOUBLE_MASK )=0A- = vcpu_must_have_sse2();=0A+ host_and_vcpu_must_have(sse2);=0A= else=0A- vcpu_must_have_sse();=0A+ = host_and_vcpu_must_have(sse);=0A ea.bytes =3D 16;=0A = SET_SSE_PREFIX(buf[0], vex.pfx);=0A get_fpu(X86EMUL_FPU_xm= m, &fic);=0A@@ -4128,7 +4144,7 @@ x86_emulate(=0A = ((vex.reg !=3D 0xf) &&=0A ((ea.type =3D=3D OP_MEM) = ||=0A !(vex.pfx & VEX_PREFIX_SCALAR_MASK))));=0A- = vcpu_must_have_avx();=0A+ host_and_vcpu_must_have(avx);= =0A get_fpu(X86EMUL_FPU_ymm, &fic);=0A ea.bytes = =3D 16 << vex.l;=0A }=0A@@ -4361,16 +4377,16 @@ x86_emulate(=0A = {=0A case vex_66:=0A case vex_f3:=0A- = vcpu_must_have_sse2();=0A+ host_and_vcpu_must_hav= e(sse2);=0A buf[0] =3D 0x66; /* movdqa */=0A = get_fpu(X86EMUL_FPU_xmm, &fic);=0A ea.bytes =3D 16;=0A = break;=0A case vex_none:=0A if ( = b !=3D 0xe7 )=0A- vcpu_must_have_mmx();=0A+ = host_and_vcpu_must_have(mmx);=0A else=0A- = vcpu_must_have_sse();=0A+ host_and_vcpu_must_ha= ve(sse);=0A get_fpu(X86EMUL_FPU_mmx, &fic);=0A = ea.bytes =3D 8;=0A break;=0A@@ -4382,7 +4398,7 @@ = x86_emulate(=0A {=0A fail_if((vex.opcx !=3D vex_0f) || = (vex.reg !=3D 0xf) ||=0A ((vex.pfx !=3D vex_66) && = (vex.pfx !=3D vex_f3)));=0A- vcpu_must_have_avx();=0A+ = host_and_vcpu_must_have(avx);=0A get_fpu(X86EMUL_FPU_ymm, = &fic);=0A ea.bytes =3D 16 << vex.l;=0A }=0A@@ -4688,7 = +4704,7 @@ x86_emulate(=0A generate_exception_if((modrm_reg & 7) = !=3D 1, EXC_UD, -1);=0A generate_exception_if(ea.type !=3D OP_MEM, = EXC_UD, -1);=0A if ( op_bytes =3D=3D 8 )=0A- vcpu_must_h= ave_cx16();=0A+ host_and_vcpu_must_have(cx16);=0A = op_bytes *=3D 2;=0A =0A /* Get actual old value. */=0A --=__Part685FD0B4.1__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwOi8vbGlzdHMueGVuLm9y Zy94ZW4tZGV2ZWwK --=__Part685FD0B4.1__=--