From: "Michał Leszczyński" <michal.leszczynski@cert.pl>
To: xen-devel@lists.xenproject.org
Cc: "Kang, Luwei" <luwei.kang@intel.com>, "Wei Liu" <wl@xen.org>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Tamas K Lengyel" <tamas.lengyel@intel.com>,
"Roger Pau Monné" <roger.pau@citrix.com>
Subject: [PATCH v3 2/7] x86/vmx: add Intel PT MSR definitions
Date: Mon, 22 Jun 2020 20:10:42 +0200 (CEST) [thread overview]
Message-ID: <639255187.11443691.1592849442180.JavaMail.zimbra@cert.pl> (raw)
In-Reply-To: <1617453791.11443328.1592849168658.JavaMail.zimbra@cert.pl>
Define constants related to Intel Processor Trace features.
Signed-off-by: Michal Leszczynski <michal.leszczynski@cert.pl>
---
xen/include/asm-x86/msr-index.h | 37 +++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index b328a47ed8..0203029be9 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -69,6 +69,43 @@
#define MSR_MCU_OPT_CTRL 0x00000123
#define MCU_OPT_CTRL_RNGDS_MITG_DIS (_AC(1, ULL) << 0)
+/* Intel PT MSRs */
+#define MSR_RTIT_OUTPUT_BASE 0x00000560
+
+#define MSR_RTIT_OUTPUT_MASK 0x00000561
+
+#define MSR_RTIT_CTL 0x00000570
+#define RTIT_CTL_TRACEEN (_AC(1, ULL) << 0)
+#define RTIT_CTL_CYCEN (_AC(1, ULL) << 1)
+#define RTIT_CTL_OS (_AC(1, ULL) << 2)
+#define RTIT_CTL_USR (_AC(1, ULL) << 3)
+#define RTIT_CTL_PWR_EVT_EN (_AC(1, ULL) << 4)
+#define RTIT_CTL_FUP_ON_PTW (_AC(1, ULL) << 5)
+#define RTIT_CTL_FABRIC_EN (_AC(1, ULL) << 6)
+#define RTIT_CTL_CR3_FILTER (_AC(1, ULL) << 7)
+#define RTIT_CTL_TOPA (_AC(1, ULL) << 8)
+#define RTIT_CTL_MTC_EN (_AC(1, ULL) << 9)
+#define RTIT_CTL_TSC_EN (_AC(1, ULL) << 10)
+#define RTIT_CTL_DIS_RETC (_AC(1, ULL) << 11)
+#define RTIT_CTL_PTW_EN (_AC(1, ULL) << 12)
+#define RTIT_CTL_BRANCH_EN (_AC(1, ULL) << 13)
+#define RTIT_CTL_MTC_FREQ (_AC(0x0F, ULL) << 14)
+#define RTIT_CTL_CYC_THRESH (_AC(0x0F, ULL) << 19)
+#define RTIT_CTL_PSB_FREQ (_AC(0x0F, ULL) << 24)
+#define RTIT_CTL_ADDR(n) (_AC(0x0F, ULL) << (32 + (4 * (n))))
+
+#define MSR_RTIT_STATUS 0x00000571
+#define RTIT_STATUS_FILTER_EN (_AC(1, ULL) << 0)
+#define RTIT_STATUS_CONTEXT_EN (_AC(1, ULL) << 1)
+#define RTIT_STATUS_TRIGGER_EN (_AC(1, ULL) << 2)
+#define RTIT_STATUS_ERROR (_AC(1, ULL) << 4)
+#define RTIT_STATUS_STOPPED (_AC(1, ULL) << 5)
+#define RTIT_STATUS_BYTECNT (_AC(0x1FFFF, ULL) << 32)
+
+#define MSR_RTIT_CR3_MATCH 0x00000572
+#define MSR_RTIT_ADDR_A(n) (0x00000580 + (n) * 2)
+#define MSR_RTIT_ADDR_B(n) (0x00000581 + (n) * 2)
+
#define MSR_U_CET 0x000006a0
#define MSR_S_CET 0x000006a2
#define CET_SHSTK_EN (_AC(1, ULL) << 0)
--
2.20.1
next prev parent reply other threads:[~2020-06-22 18:11 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-22 18:06 [PATCH v3 0/7] Implement support for external IPT monitoring Michał Leszczyński
2020-06-22 18:10 ` [PATCH v3 1/7] memory: batch processing in acquire_resource() Michał Leszczyński
2020-06-22 18:10 ` Michał Leszczyński [this message]
2020-06-22 18:11 ` [PATCH v3 3/7] x86/vmx: add IPT cpu feature Michał Leszczyński
2020-06-22 18:11 ` [PATCH v3 4/7] x86/vmx: add do_vmtrace_op Michał Leszczyński
2020-06-23 11:54 ` Andrew Cooper
2020-06-29 9:52 ` Michał Leszczyński
2020-06-22 18:12 ` [PATCH v3 5/7] tools/libxc: add xc_vmtrace_* functions Michał Leszczyński
2020-06-26 11:50 ` Wei Liu
2020-06-22 18:12 ` [PATCH v3 6/7] tools/libxl: add vmtrace_pt_size parameter Michał Leszczyński
2020-06-26 11:52 ` Wei Liu
2020-06-22 18:12 ` [PATCH v3 7/7] tools/proctrace: add proctrace tool Michał Leszczyński
2020-06-23 9:35 ` Tamas K Lengyel
2020-06-26 11:48 ` Wei Liu
2020-06-26 13:24 ` Ian Jackson
2020-06-29 15:27 ` Tamas K Lengyel
2020-07-01 11:01 ` Ian Jackson
2020-06-22 18:19 ` [PATCH v3 0/7] Implement support for external IPT monitoring Michał Leszczyński
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