[PATCH v2 1/2] x86/Intel: Sapphire Rapids Xeons also support PPIN

From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: [PATCH v2 1/2] x86/Intel: Sapphire Rapids Xeons also support PPIN
Date: Thu, 20 Jan 2022 15:16:35 +0100	[thread overview]
Message-ID: <0a8981c6-b3fe-c805-f45b-b6da5d0aa1af@suse.com> (raw)
In-Reply-To: <64a5a3ac-8f4c-b13d-0b7d-4c4ec15e2721@suse.com>

This is as per Linux commit a331f5fdd36d ("x86/mce: Add Xeon Sapphire
Rapids to list of CPUs that support PPIN") just in case a subsequent
change making use of the respective new CPUID bit doesn't cover this
model.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
It is unclear to me whether this change is actually made obsolete by the
subsequent one adding support for the respective new CPUID bit.

It also continues to be unclear for which CPU models, if any, the
PPIN_CAP bit in PLATFORM_INFO could be used in favor of a model check.
---
v2: New.

--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -873,6 +873,7 @@ static void intel_init_ppin(const struct
     case 0x57: /* Knights Landing */
     case 0x6a: /* Icelake X */
     case 0x85: /* Knights Mill */
+    case 0x8f: /* Sapphire Rapids X */
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, val) )


