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From: Richard Gong <richard.gong@linux.intel.com>
To: Moritz Fischer <mdf@kernel.org>
Cc: trix@redhat.com, linux-fpga@vger.kernel.org,
	linux-kernel@vger.kernel.org, dinguyen@kernel.org,
	sridhar.rajagopal@intel.com,
	Richard Gong <richard.gong@intel.com>
Subject: Re: [PATCHv1 4/4] fpga: stratix10-soc: entend driver for bitstream authentication
Date: Mon, 16 Nov 2020 08:39:36 -0600	[thread overview]
Message-ID: <0eb7fa0d-30e6-099f-d104-8a9aea7d8030@linux.intel.com> (raw)
In-Reply-To: <20201115191936.GA283592@epycbox.lan>


Hi Moritz,

On 11/15/20 1:19 PM, Moritz Fischer wrote:
> On Thu, Nov 12, 2020 at 12:06:43PM -0600, richard.gong@linux.intel.com wrote:
>> From: Richard Gong <richard.gong@intel.com>
>>
>> Exten FPGA manager driver to support FPGA bitstream authentication on
> Nit: Extend

Sorry, I will fix that in version 2.

>> Intel SocFPGA platforms.
>>
>> Signed-off-by: Richard Gong <richard.gong@intel.com>
>> ---
>>   drivers/fpga/stratix10-soc.c | 5 ++++-
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
>> index 657a70c..8a59365 100644
>> --- a/drivers/fpga/stratix10-soc.c
>> +++ b/drivers/fpga/stratix10-soc.c
>> @@ -185,7 +185,10 @@ static int s10_ops_write_init(struct fpga_manager *mgr,
>>   	ctype.flags = 0;
>>   	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
>>   		dev_dbg(dev, "Requesting partial reconfiguration.\n");
>> -		ctype.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL);
>> +		ctype.flags |= FPGA_MGR_PARTIAL_RECONFIG;
> I think we had this discussion during the original review of the
> stratix10-soc driver?

Yes, we discussed before.

> 
> Wasn't the point of using the BIT() to not assume alignment of FPGA_MGR
> flags and firmware structure?
> 

Yes, we should use BIT().

> The FPGA_MGR_* bits are kernel internal and can therefore change, it
> would be unfortunate to end up in a situation where this breaks the FW
> interface (assuming firmware uses the value in pass-through which it
> looks like is what is happening).

In that case, I should use the flag defined in stratix10-soc driver driver.

> 
>> +	} else if (info->flags & FPGA_MGR_BITSTREM_AUTHENTICATION) {
>> +		dev_dbg(dev, "Requesting bitstream authentication.\n");
>> +		ctype.flags |= FPGA_MGR_BITSTREM_AUTHENTICATION;
> Do you want to change this to BIT(COMMAND_AUTHENTICATE_BITSTREAM) or
> something like that?

OK, I will change to BIT(COMMAND_AUTHENTICATE_BITSTREAM).

Regards,
Richard

>>   	} else {
>>   		dev_dbg(dev, "Requesting full reconfiguration.\n");
>>   	}
>> -- 
>> 2.7.4
>>
> 
> Thanks,
> Moritz
> 

  reply	other threads:[~2020-11-16 14:18 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-12 18:06 [PATCHv1 0/4] Extend FPGA manager and region drivers for richard.gong
2020-11-12 18:06 ` [PATCHv1 1/4] fpga: fpga-mgr: add FPGA_MGR_BITSTREM_AUTHENTICATION flag richard.gong
2020-11-13 20:24   ` Tom Rix
2020-11-14 14:30     ` Richard Gong
2020-11-14 15:53       ` Tom Rix
2020-11-16 13:39         ` Richard Gong
2020-11-12 18:06 ` [PATCHv1 2/4] fpga: of-fpga-region: add authenticate-fpga-config property richard.gong
2020-11-13 20:25   ` Tom Rix
2020-11-12 18:06 ` [PATCHv1 3/4] dt-bindings: fpga: " richard.gong
2020-11-13 20:28   ` Tom Rix
2020-11-14 14:52     ` Richard Gong
2020-11-14 15:59       ` Tom Rix
2020-11-16 13:50         ` Richard Gong
2020-11-16 15:11           ` Tom Rix
2020-11-15 19:21   ` Moritz Fischer
2020-11-16  2:47     ` Xu Yilun
2020-11-16 14:14       ` Richard Gong
2020-11-17  2:24         ` Xu Yilun
2020-11-17 15:39           ` Richard Gong
2020-11-18  5:47             ` Xu Yilun
2020-11-18 13:38               ` Richard Gong
2020-11-19 11:14                 ` Xu Yilun
2020-11-16 13:59     ` Richard Gong
2020-11-12 18:06 ` [PATCHv1 4/4] fpga: stratix10-soc: entend driver for bitstream authentication richard.gong
2020-11-13 20:31   ` Tom Rix
2020-11-14 14:55     ` Richard Gong
2020-11-15 19:19   ` Moritz Fischer
2020-11-16 14:39     ` Richard Gong [this message]
2020-11-16  2:41 ` [PATCHv1 0/4] Extend FPGA manager and region drivers for Xu Yilun
2020-11-16 14:02   ` Richard Gong

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