[PATCH 1/4] drm/i915: Use HW watchdog for each batch

From: Ben Widawsky <ben@bwidawsk.net>
To: intel-gfx@lists.freedesktop.org
Cc: Ben Widawsky <ben@bwidawsk.net>
Subject: [PATCH 1/4] drm/i915: Use HW watchdog for each batch
Date: Mon, 16 Jul 2012 11:51:56 -0700	[thread overview]
Message-ID: <1342464719-8790-2-git-send-email-ben@bwidawsk.net> (raw)
In-Reply-To: <1342464719-8790-1-git-send-email-ben@bwidawsk.net>

The HW watchdog exists for all the rings. It's just a register, but if
we writing in the command stream it has the effect we want of generating
interrupts if a given batch is taking too long.

Unfortunately, our hardware doesn't support interrupts on the blit ring.
We still need the software watchdog for that.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h         |  2 +-
 drivers/gpu/drm/i915/i915_reg.h         |  2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 26 +++++++++++++++++++++++++-
 3 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 627fe35..0a13b22 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -430,7 +430,7 @@ typedef struct drm_i915_private {
 	int num_pch_pll;
 
 	/* For hangcheck timer */
-#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
+#define DRM_I915_HANGCHECK_PERIOD 3000 /* in ms */
 	struct timer_list hangcheck_timer;
 	int hangcheck_count;
 	uint32_t last_acthd[I915_NUM_RINGS];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc82871..195154b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -449,6 +449,8 @@
 #define RING_ACTHD(base)	((base)+0x74)
 #define RING_NOPID(base)	((base)+0x94)
 #define RING_IMR(base)		((base)+0xa8)
+#define RING_WATCHDOG_CTL(base) ((base)+0x178)
+#define RING_WATCHDOG_THRESH(base) ((base)+0x17c)
 #define   TAIL_ADDR		0x001FFFF8
 #define   HEAD_WRAP_COUNT	0xFFE00000
 #define   HEAD_WRAP_ONE		0x00200000
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ddc4859..f61b4a0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1038,6 +1038,9 @@ static int intel_init_ring_buffer(struct drm_device *dev,
 		goto err_unpin;
 	}
 
+	I915_WRITE(RING_WATCHDOG_CTL(ring->mmio_base), UINT_MAX);
+	I915_WRITE(RING_WATCHDOG_THRESH(ring->mmio_base), UINT_MAX);
+
 	ret = ring->init(ring);
 	if (ret)
 		goto err_unmap;
@@ -1318,19 +1321,40 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
 	return 0;
 }
 
+#define PERIOD_NS	80
+#define WATCHDOG_TIMEOUT(timeout_ms) (DIV_ROUND_UP(timeout_ms * NSEC_PER_MSEC, PERIOD_NS))
+/* this should be less than the i915 software watchdog */
+#define DEFAULT_WATCHDOG_TIMEOUT WATCHDOG_TIMEOUT(DRM_I915_HANGCHECK_PERIOD / 2)
+
 static int
 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 			      u32 offset, u32 len)
 {
 	int ret;
 
-	ret = intel_ring_begin(ring, 2);
+	ret = intel_ring_begin(ring, 14);
 	if (ret)
 		return ret;
 
+	intel_ring_emit(ring, MI_NOOP);
+	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+	intel_ring_emit(ring, RING_WATCHDOG_THRESH(ring->mmio_base));
+	intel_ring_emit(ring, DEFAULT_WATCHDOG_TIMEOUT);
+	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+	intel_ring_emit(ring, RING_WATCHDOG_CTL(ring->mmio_base));
+	intel_ring_emit(ring, 0);
+
+	/* add breadcrumb here */
+
 	intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
 	/* bit0-7 is the length on GEN6+ */
 	intel_ring_emit(ring, offset);
+
+	intel_ring_emit(ring, MI_NOOP);
+	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+	intel_ring_emit(ring, RING_WATCHDOG_CTL(ring->mmio_base));
+	intel_ring_emit(ring, UINT_MAX);
+
 	intel_ring_advance(ring);
 
 	return 0;
-- 
1.7.11.2
