From: Huacai Chen <chenhuacai@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>,
Huacai Chen <chenhc@lemote.com>, Hongliang Tao <taohl@lemote.com>,
Hua Yan <yanh@lemote.com>
Subject: [PATCH V5 07/18] MIPS: Loongson 3: Add IRQ init and dispatch support.
Date: Sat, 11 Aug 2012 17:32:12 +0800 [thread overview]
Message-ID: <1344677543-22591-8-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1344677543-22591-1-git-send-email-chenhc@lemote.com>
IRQ routing path of Loongson-3:
Devices(most) --> I8259 --> HT Controller --> IRQ Routing Table --> CPU
^
|
Device(legacy devices such as UART) --> Bonito ---|
IRQ Routing Table route 32 INTs to CPU's INT0~INT3(IP2~IP5 of CP0), 32
INTs include 16 HT INTs(mostly), 4 PCI INTs, 1 LPC INT, etc. IP6 is used
for IPI and IP7 is used for internal MIPS timer. LOONGSON_INT_ROUTER_*
are IRQ Routing Table registers.
I8259 IRQs are 1:1 mapped to HT1 INTs. LOONGSON_HT1_* are configuration
registers of HT1 controller.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
---
arch/mips/include/asm/mach-loongson/irq.h | 24 +++++++
arch/mips/include/asm/mach-loongson/loongson.h | 9 +++
arch/mips/loongson/Makefile | 6 ++
arch/mips/loongson/loongson-3/Makefile | 4 +
arch/mips/loongson/loongson-3/irq.c | 87 ++++++++++++++++++++++++
5 files changed, 130 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/include/asm/mach-loongson/irq.h
create mode 100644 arch/mips/loongson/loongson-3/Makefile
create mode 100644 arch/mips/loongson/loongson-3/irq.c
diff --git a/arch/mips/include/asm/mach-loongson/irq.h b/arch/mips/include/asm/mach-loongson/irq.h
new file mode 100644
index 0000000..4787cd0
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/irq.h
@@ -0,0 +1,24 @@
+#ifndef __ASM_MACH_LOONGSON_IRQ_H_
+#define __ASM_MACH_LOONGSON_IRQ_H_
+
+#include <boot_param.h>
+
+/* cpu core interrupt numbers */
+#define MIPS_CPU_IRQ_BASE 56
+
+#ifdef CONFIG_CPU_LOONGSON3
+
+#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* uart */
+#define LOONGSON_I8259_IRQ (MIPS_CPU_IRQ_BASE + 3) /* i8259 */
+#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
+
+#define LOONGSON_HT1_CFG_BASE ht_control_base
+#define LOONGSON_HT1_INT_VECTOR_BASE LOONGSON_HT1_CFG_BASE + 0x80
+#define LOONGSON_HT1_INT_EN_BASE LOONGSON_HT1_CFG_BASE + 0xa0
+#define LOONGSON_HT1_INT_VECTOR(n) LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * n)
+#define LOONGSON_HT1_INTN_EN(n) LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * n)
+
+#endif
+
+#include_next <irq.h>
+#endif /* __ASM_MACH_LOONGSON_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 960811a..f573e47 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -62,6 +62,12 @@ extern int mach_i8259_irq(void);
#define LOONGSON_REG(x) \
(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+#define LOONGSON3_REG8(base, x) \
+ (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
+
+#define LOONGSON3_REG32(base, x) \
+ (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
+
#define LOONGSON_IRQ_BASE 32
#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
@@ -87,6 +93,9 @@ static inline void do_perfcnt_IRQ(void)
#define LOONGSON_REG_BASE 0x1fe00000
#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
+#define LOONGSON3_REG_BASE 0x3ff00000
+#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
#define LOONGSON_LIO1_BASE 0x1ff00000
#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile
index 2b76cb0..b1e4f05 100644
--- a/arch/mips/loongson/Makefile
+++ b/arch/mips/loongson/Makefile
@@ -15,3 +15,9 @@ obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
#
obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
+
+#
+# All Loongson-3 family machines
+#
+
+obj-$(CONFIG_CPU_LOONGSON3) += loongson-3/
diff --git a/arch/mips/loongson/loongson-3/Makefile b/arch/mips/loongson/loongson-3/Makefile
new file mode 100644
index 0000000..b9968cd
--- /dev/null
+++ b/arch/mips/loongson/loongson-3/Makefile
@@ -0,0 +1,4 @@
+#
+# Makefile for Loongson-3 family machines
+#
+obj-y += irq.o
diff --git a/arch/mips/loongson/loongson-3/irq.c b/arch/mips/loongson/loongson-3/irq.c
new file mode 100644
index 0000000..27aef31
--- /dev/null
+++ b/arch/mips/loongson/loongson-3/irq.c
@@ -0,0 +1,87 @@
+#include <loongson.h>
+#include <irq.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+
+#define LOONGSON_INT_ROUTER_OFFSET 0x1400
+#define LOONGSON_INT_ROUTER_INTEN LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
+#define LOONGSON_INT_ROUTER_INTENSET LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
+#define LOONGSON_INT_ROUTER_INTENCLR LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
+#define LOONGSON_INT_ROUTER_ENTRY(n) LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
+#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
+#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
+
+#define LOONGSON_INT_CORE0_INT0 0x11 /* route to int 0 of core 0 */
+#define LOONGSON_INT_CORE0_INT1 0x21 /* route to int 1 of core 0 */
+
+extern void loongson3_ipi_interrupt(struct pt_regs *regs);
+
+static void ht_irqdispatch(void)
+{
+ unsigned int i, irq;
+ unsigned int ht_irq[] = {1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
+
+ irq = LOONGSON_HT1_INT_VECTOR(0);
+ LOONGSON_HT1_INT_VECTOR(0) = irq;
+
+ for (i = 0; i < (sizeof(ht_irq) / sizeof(*ht_irq)); i++) {
+ if (irq & (0x1 << ht_irq[i]))
+ do_IRQ(ht_irq[i]);
+ }
+}
+
+void mach_irq_dispatch(unsigned int pending)
+{
+ if (pending & CAUSEF_IP7)
+ do_IRQ(LOONGSON_TIMER_IRQ);
+#if defined(CONFIG_SMP)
+ else if (pending & CAUSEF_IP6)
+ loongson3_ipi_interrupt(NULL);
+#endif
+ else if (pending & CAUSEF_IP3)
+ ht_irqdispatch();
+ else if (pending & CAUSEF_IP2)
+ do_IRQ(LOONGSON_UART_IRQ);
+ else {
+ printk(KERN_ERR "%s : spurious interrupt\n", __func__);
+ spurious_interrupt();
+ }
+}
+
+static struct irqaction cascade_irqaction = {
+ .handler = no_action,
+ .name = "cascade",
+};
+
+void irq_router_init(void)
+{
+ int i;
+
+ /* route LPC int to cpu core0 int 0 */
+ LOONGSON_INT_ROUTER_LPC = LOONGSON_INT_CORE0_INT0;
+ /* route HT1 int0 ~ int7 to cpu core0 INT1*/
+ for (i = 0; i < 8; i++)
+ LOONGSON_INT_ROUTER_HT1(i) = LOONGSON_INT_CORE0_INT1;
+ /* enable HT1 interrupt */
+ LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
+ /* enable router interrupt intenset */
+ LOONGSON_INT_ROUTER_INTENSET = LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
+}
+
+void __init mach_init_irq(void)
+{
+ clear_c0_status(ST0_IM | ST0_BEV);
+
+ irq_router_init();
+ mips_cpu_irq_init();
+ init_i8259_irqs();
+
+ /* setup i8259 irq */
+ setup_irq(LOONGSON_I8259_IRQ, &cascade_irqaction);
+
+ set_c0_status(STATUSF_IP2 | STATUSF_IP6);
+}
--
1.7.7.3
next prev parent reply other threads:[~2012-08-11 9:34 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-11 9:32 [PATCH V5 00/16] MIPS: Add Loongson-3 based machines support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 01/18] MIPS: Loongson: Add basic Loongson-3 definition Huacai Chen
2012-08-12 5:51 ` John Crispin
2012-08-15 19:36 ` Ralf Baechle
2012-08-16 0:39 ` Huacai Chen
2012-08-11 9:32 ` [PATCH V5 02/18] MIPS: Loongson: Add basic Loongson-3 CPU support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 03/18] MIPS: Loongson 3: Add Lemote-3A machtypes definition Huacai Chen
2012-08-11 9:32 ` [PATCH V5 04/18] MIPS: Loongson: Make Loongson-3 to use BCD format for RTC Huacai Chen
2012-08-12 6:06 ` John Crispin
2012-08-11 9:32 ` [PATCH V5 05/18] MIPS: Loongson: Add UEFI-like firmware interface support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 06/18] MIPS: Loongson 3: Add HT-linked PCI support Huacai Chen
2012-08-11 9:32 ` Huacai Chen [this message]
2012-08-11 9:32 ` [PATCH V5 08/18] MIPS: Loongson 3: Add serial port support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 09/18] MIPS: Loongson: Add swiotlb to support big memory (>4GB) Huacai Chen
2012-08-12 6:17 ` John Crispin
2012-08-13 17:54 ` Konrad Rzeszutek Wilk
2012-08-14 2:29 ` Huacai Chen
2012-08-14 5:57 ` Huacai Chen
2012-08-14 16:26 ` David Daney
2012-08-14 16:26 ` David Daney
2012-08-15 2:18 ` Huacai Chen
2012-08-15 20:24 ` Ralf Baechle
2012-08-16 3:19 ` Huacai Chen
2012-08-11 9:32 ` [PATCH V5 10/18] MIPS: Loongson: Add Loongson-3 Kconfig options Huacai Chen
2012-08-12 6:20 ` John Crispin
2012-08-11 9:32 ` [PATCH V5 11/18] drm/radeon: Include swiotlb.h if SWIOTLB configured Huacai Chen
2012-08-11 9:32 ` [PATCH V5 12/18] drm: Handle io prot correctly for MIPS Huacai Chen
2012-08-11 9:32 ` [PATCH V5 13/18] drm: Define SAREA_MAX for Loongson (PageSize = 16KB) Huacai Chen
2012-08-15 21:31 ` Ralf Baechle
2012-08-16 0:43 ` Huacai Chen
2012-08-16 1:58 ` Matt Turner
2012-08-16 1:58 ` Matt Turner
2012-08-16 3:20 ` Huacai Chen
2012-08-11 9:32 ` [PATCH V5 14/18] ALSA: HDA: Make hda sound card usable for Loongson Huacai Chen
2012-08-11 9:32 ` Huacai Chen
2012-08-13 8:00 ` [alsa-devel] " Takashi Iwai
2012-08-13 8:00 ` Takashi Iwai
2012-08-13 8:00 ` [alsa-devel] " Takashi Iwai
2012-08-13 8:22 ` Huacai Chen
2012-08-13 8:22 ` Huacai Chen
2012-08-11 9:32 ` [PATCH V5 15/18] MIPS: Loongson 3: Add Loongson-3 SMP support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 16/18] MIPS: Loongson 3: Add CPU hotplug support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 17/18] MIPS: Fix poweroff failure when HOTPLUG_CPU configured Huacai Chen
2012-08-11 9:32 ` [PATCH V5 18/18] MIPS: Loongson: Add a Loongson-3 default config file Huacai Chen
2012-08-12 6:13 ` [PATCH V5 00/16] MIPS: Add Loongson-3 based machines support John Crispin
2012-08-12 8:10 ` Huacai Chen
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