From: ville.syrjala@linux.intel.com
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 44/51] drm/i915: Split sprite update_plane() into calc+commit phases
Date: Thu, 25 Oct 2012 21:05:47 +0300 [thread overview]
Message-ID: <1351188354-24233-45-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1351188354-24233-1-git-send-email-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Separate the part that calculates the register values from the part that
writes the registers. This will be useful in the atomic page flip code.
Also move the watermark magic into a prepare function that can be
performed outside the critical parts of the atomic page flip code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 5 +
drivers/gpu/drm/i915/intel_sprite.c | 398 ++++++++++++++++++++++-------------
2 files changed, 259 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1389eeb..6ab8f65 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -252,6 +252,11 @@ struct intel_plane {
struct drm_intel_sprite_colorkey *key);
void (*get_colorkey)(struct drm_plane *plane,
struct drm_intel_sprite_colorkey *key);
+ void (*calc)(struct drm_plane *plane, struct drm_framebuffer *fb,
+ const struct intel_plane_coords *clip);
+ void (*prepare)(struct drm_plane *plane);
+ void (*commit)(struct drm_plane *plane);
+ struct intel_plane_regs regs;
};
struct intel_watermark_params {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index fee6f17..06d62e70 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -187,14 +187,12 @@ int intel_check_plane(const struct drm_plane *plane,
}
static void
-ivb_update_plane(struct drm_plane *plane,
- struct drm_framebuffer *fb,
- const struct intel_plane_coords *coords)
+ivb_calc_plane(struct drm_plane *plane,
+ struct drm_framebuffer *fb,
+ const struct intel_plane_coords *coords)
{
- struct drm_device *dev = plane->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane);
- const struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
+ const struct drm_i915_gem_object *obj;
int crtc_x = coords->crtc_x;
int crtc_y = coords->crtc_y;
unsigned int crtc_w = coords->crtc_w;
@@ -203,47 +201,55 @@ ivb_update_plane(struct drm_plane *plane,
uint32_t y = coords->src_y;
uint32_t src_w = coords->src_w;
uint32_t src_h = coords->src_h;
- int pipe = intel_plane->pipe;
- u32 sprctl, sprscale = 0;
- int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int pixel_size;
+ struct intel_plane_regs *regs = &intel_plane->regs;
+
+ if (!coords->visible) {
+ regs->cntr &= ~SPRITE_ENABLE;
+ /* Disable the scaler */
+ regs->scale = 0;
+ return;
+ }
- sprctl = I915_READ(SPRCTL(pipe));
+ obj = to_intel_framebuffer(fb)->obj;
+ pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
/* Mask out pixel format bits in case we change it */
- sprctl &= ~SPRITE_PIXFORMAT_MASK;
- sprctl &= ~SPRITE_RGB_ORDER_RGBX;
- sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
- sprctl &= ~SPRITE_TILED;
+ regs->cntr &= ~(SPRITE_PIXFORMAT_MASK |
+ SPRITE_RGB_ORDER_RGBX |
+ SPRITE_YUV_BYTE_ORDER_MASK |
+ SPRITE_TILED |
+ SPRITE_ENABLE);
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR8888:
- sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
+ regs->cntr |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
break;
case DRM_FORMAT_XRGB8888:
- sprctl |= SPRITE_FORMAT_RGBX888;
+ regs->cntr |= SPRITE_FORMAT_RGBX888;
break;
case DRM_FORMAT_YUYV:
- sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
+ regs->cntr |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
break;
case DRM_FORMAT_YVYU:
- sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
+ regs->cntr |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
break;
case DRM_FORMAT_UYVY:
- sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
+ regs->cntr |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
break;
case DRM_FORMAT_VYUY:
- sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
+ regs->cntr |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
break;
default:
BUG();
}
if (obj->tiling_mode != I915_TILING_NONE)
- sprctl |= SPRITE_TILED;
+ regs->cntr |= SPRITE_TILED;
/* must disable */
- sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
- sprctl |= SPRITE_ENABLE;
+ regs->cntr |= SPRITE_TRICKLE_FEED_DISABLE;
+ regs->cntr |= SPRITE_ENABLE;
/* Sizes are 0 based */
src_w--;
@@ -251,20 +257,68 @@ ivb_update_plane(struct drm_plane *plane,
crtc_w--;
crtc_h--;
- intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
+ regs->scale = 0;
+ if (crtc_w != src_w || crtc_h != src_h)
+ regs->scale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
+
+ regs->stride = fb->pitches[0];
+ regs->pos = (crtc_y << 16) | crtc_x;
+ if (obj->tiling_mode != I915_TILING_NONE) {
+ y += fb->offsets[0] / fb->pitches[0];
+ x += fb->offsets[0] % fb->pitches[0] / pixel_size;
+
+ regs->tileoff = (y << 16) | x;
+ } else
+ regs->linoff = fb->offsets[0] + y * fb->pitches[0] + x * pixel_size;
+ regs->size = (crtc_h << 16) | crtc_w;
+ regs->surf = I915_LO_DISPBASE(regs->surf) | obj->gtt_offset;
+}
+
+static void
+ivb_commit_plane(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ int pipe = intel_plane->pipe;
+ const struct intel_plane_regs *regs = &intel_plane->regs;
+
+ I915_WRITE(SPRKEYVAL(pipe), regs->keyval);
+ I915_WRITE(SPRKEYMAX(pipe), regs->keymaxval);
+ I915_WRITE(SPRKEYMSK(pipe), regs->keymsk);
+ I915_WRITE(SPRSTRIDE(pipe), regs->stride);
+ I915_WRITE(SPRPOS(pipe), regs->pos);
+ I915_WRITE(SPRTILEOFF(pipe), regs->tileoff);
+ I915_WRITE(SPRLINOFF(pipe), regs->linoff);
+ I915_WRITE(SPRSIZE(pipe), regs->size);
+ I915_WRITE(SPRSCALE(pipe), regs->scale);
+ I915_WRITE(SPRCTL(pipe), regs->cntr);
+ I915_WRITE(SPRSURF(pipe), regs->surf);
+}
+
+static void
+ivb_prepare_plane(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ int pipe = intel_plane->pipe;
+ int pixel_size = plane->fb ? drm_format_plane_cpp(plane->fb->pixel_format, 0) : 0;
+ const struct intel_plane_regs *regs = &intel_plane->regs;
+
+ intel_update_sprite_watermarks(dev, pipe, regs->size & 0xffff, pixel_size);
/*
* IVB workaround: must disable low power watermarks for at least
* one frame before enabling scaling. LP watermarks can be re-enabled
* when scaling is disabled.
*/
- if (crtc_w != src_w || crtc_h != src_h) {
+ if (regs->scale & SPRITE_SCALE_ENABLE) {
if (!dev_priv->sprite_scaling_enabled) {
dev_priv->sprite_scaling_enabled = true;
intel_update_watermarks(dev);
intel_wait_for_vblank(dev, pipe);
}
- sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
} else {
if (dev_priv->sprite_scaling_enabled) {
dev_priv->sprite_scaling_enabled = false;
@@ -272,24 +326,21 @@ ivb_update_plane(struct drm_plane *plane,
intel_update_watermarks(dev);
}
}
+}
- I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
- I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
- if (obj->tiling_mode != I915_TILING_NONE) {
- y += fb->offsets[0] / fb->pitches[0];
- x += fb->offsets[0] % fb->pitches[0] / pixel_size;
-
- I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
- } else {
- unsigned long offset;
+static void
+ivb_update_plane(struct drm_plane *plane,
+ struct drm_framebuffer *fb,
+ const struct intel_plane_coords *coords)
+{
+ struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ int pipe = intel_plane->pipe;
- offset = fb->offsets[0] + y * fb->pitches[0] + x * pixel_size;
- I915_WRITE(SPRLINOFF(pipe), offset);
- }
- I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
- I915_WRITE(SPRSCALE(pipe), sprscale);
- I915_WRITE(SPRCTL(pipe), sprctl);
- I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);
+ ivb_calc_plane(plane, fb, coords);
+ ivb_prepare_plane(plane);
+ ivb_commit_plane(plane);
POSTING_READ(SPRSURF(pipe));
}
@@ -300,12 +351,12 @@ ivb_disable_plane(struct drm_plane *plane)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane);
int pipe = intel_plane->pipe;
+ struct intel_plane_regs *regs = &intel_plane->regs;
- I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
+ regs->cntr &= ~SPRITE_ENABLE;
/* Can't leave the scaler enabled... */
- I915_WRITE(SPRSCALE(pipe), 0);
- /* Activate double buffered register update */
- I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
+ regs->scale = 0;
+ ivb_commit_plane(plane);
POSTING_READ(SPRSURF(pipe));
dev_priv->sprite_scaling_enabled = false;
@@ -318,63 +369,52 @@ ivb_update_colorkey(struct drm_plane *plane,
{
struct drm_device *dev = plane->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_plane *intel_plane;
- u32 sprctl;
- int ret = 0;
-
- intel_plane = to_intel_plane(plane);
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ struct intel_plane_regs *regs = &intel_plane->regs;
- I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
- I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
- I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
+ regs->keyval = key->min_value;
+ regs->keymaxval = key->max_value;
+ regs->keymsk = key->channel_mask;
- sprctl = I915_READ(SPRCTL(intel_plane->pipe));
- sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
+ regs->cntr &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
if (key->flags & I915_SET_COLORKEY_DESTINATION)
- sprctl |= SPRITE_DEST_KEY;
+ regs->cntr |= SPRITE_DEST_KEY;
else if (key->flags & I915_SET_COLORKEY_SOURCE)
- sprctl |= SPRITE_SOURCE_KEY;
- I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
+ regs->cntr |= SPRITE_SOURCE_KEY;
+ ivb_commit_plane(plane);
POSTING_READ(SPRKEYMSK(intel_plane->pipe));
- return ret;
+ return 0;
}
static void
ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
{
- struct drm_device *dev = plane->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_plane *intel_plane;
- u32 sprctl;
-
- intel_plane = to_intel_plane(plane);
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ const struct intel_plane_regs *regs = &intel_plane->regs;
- key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
- key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
- key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
+ key->min_value = regs->keyval;
+ key->max_value = regs->keymaxval;
+ key->channel_mask = regs->keymsk;
key->flags = 0;
- sprctl = I915_READ(SPRCTL(intel_plane->pipe));
-
- if (sprctl & SPRITE_DEST_KEY)
+ if (regs->cntr & SPRITE_DEST_KEY)
key->flags = I915_SET_COLORKEY_DESTINATION;
- else if (sprctl & SPRITE_SOURCE_KEY)
+ else if (regs->cntr & SPRITE_SOURCE_KEY)
key->flags = I915_SET_COLORKEY_SOURCE;
else
key->flags = I915_SET_COLORKEY_NONE;
}
static void
-ilk_update_plane(struct drm_plane *plane,
- struct drm_framebuffer *fb,
- const struct intel_plane_coords *coords)
+ilk_calc_plane(struct drm_plane *plane,
+ struct drm_framebuffer *fb,
+ const struct intel_plane_coords *coords)
{
struct drm_device *dev = plane->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane);
- const struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
+ const struct drm_i915_gem_object *obj;
int crtc_x = coords->crtc_x;
int crtc_y = coords->crtc_y;
unsigned int crtc_w = coords->crtc_w;
@@ -383,47 +423,55 @@ ilk_update_plane(struct drm_plane *plane,
uint32_t y = coords->src_y;
uint32_t src_w = coords->src_w;
uint32_t src_h = coords->src_h;
- int pipe = intel_plane->pipe;
- u32 dvscntr, dvsscale;
- int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int pixel_size;
+ struct intel_plane_regs *regs = &intel_plane->regs;
+
+ if (!coords->visible) {
+ regs->cntr &= ~DVS_ENABLE;
+ /* Disable the scaler */
+ regs->scale = 0;
+ return;
+ }
- dvscntr = I915_READ(DVSCNTR(pipe));
+ obj = to_intel_framebuffer(fb)->obj;
+ pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
/* Mask out pixel format bits in case we change it */
- dvscntr &= ~DVS_PIXFORMAT_MASK;
- dvscntr &= ~DVS_RGB_ORDER_XBGR;
- dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
- dvscntr &= ~DVS_TILED;
+ regs->cntr &= ~(DVS_PIXFORMAT_MASK |
+ DVS_RGB_ORDER_XBGR |
+ DVS_YUV_BYTE_ORDER_MASK |
+ DVS_TILED |
+ DVS_ENABLE);
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR8888:
- dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
+ regs->cntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
break;
case DRM_FORMAT_XRGB8888:
- dvscntr |= DVS_FORMAT_RGBX888;
+ regs->cntr |= DVS_FORMAT_RGBX888;
break;
case DRM_FORMAT_YUYV:
- dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
+ regs->cntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
break;
case DRM_FORMAT_YVYU:
- dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
+ regs->cntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
break;
case DRM_FORMAT_UYVY:
- dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
+ regs->cntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
break;
case DRM_FORMAT_VYUY:
- dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
+ regs->cntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
break;
default:
BUG();
}
if (obj->tiling_mode != I915_TILING_NONE)
- dvscntr |= DVS_TILED;
+ regs->cntr |= DVS_TILED;
if (IS_GEN6(dev))
- dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
- dvscntr |= DVS_ENABLE;
+ regs->cntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
+ regs->cntr |= DVS_ENABLE;
/* Sizes are 0 based */
src_w--;
@@ -431,29 +479,70 @@ ilk_update_plane(struct drm_plane *plane,
crtc_w--;
crtc_h--;
- intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
-
- dvsscale = 0;
+ regs->scale = 0;
if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
- dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
+ regs->scale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
- I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
- I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
+ regs->stride = fb->pitches[0];
+ regs->pos = (crtc_y << 16) | crtc_x;
if (obj->tiling_mode != I915_TILING_NONE) {
y += fb->offsets[0] / fb->pitches[0];
x += fb->offsets[0] % fb->pitches[0] / pixel_size;
- I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
- } else {
- unsigned long offset;
+ regs->tileoff = (y << 16) | x;
+ } else
+ regs->linoff = fb->offsets[0] + y * fb->pitches[0] + x * pixel_size;
+ regs->size = (crtc_h << 16) | crtc_w;
+ regs->surf = I915_LO_DISPBASE(regs->surf) | obj->gtt_offset;
+}
- offset = fb->offsets[0] + y * fb->pitches[0] + x * pixel_size;
- I915_WRITE(DVSLINOFF(pipe), offset);
- }
- I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
- I915_WRITE(DVSSCALE(pipe), dvsscale);
- I915_WRITE(DVSCNTR(pipe), dvscntr);
- I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);
+static void
+ilk_prepare_plane(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane->dev;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ int pipe = intel_plane->pipe;
+ int pixel_size = plane->fb ? drm_format_plane_cpp(plane->fb->pixel_format, 0) : 0;
+ const struct intel_plane_regs *regs = &intel_plane->regs;
+
+ intel_update_sprite_watermarks(dev, pipe, regs->size & 0xffff, pixel_size);
+}
+
+static void
+ilk_commit_plane(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ int pipe = intel_plane->pipe;
+ const struct intel_plane_regs *regs = &intel_plane->regs;
+
+ I915_WRITE(DVSKEYVAL(pipe), regs->keyval);
+ I915_WRITE(DVSKEYMAX(pipe), regs->keymaxval);
+ I915_WRITE(DVSKEYMSK(pipe), regs->keymsk);
+ I915_WRITE(DVSSTRIDE(pipe), regs->stride);
+ I915_WRITE(DVSPOS(pipe), regs->pos);
+ I915_WRITE(DVSTILEOFF(pipe), regs->tileoff);
+ I915_WRITE(DVSLINOFF(pipe), regs->linoff);
+ I915_WRITE(DVSSIZE(pipe), regs->size);
+ I915_WRITE(DVSSCALE(pipe), regs->scale);
+ I915_WRITE(DVSCNTR(pipe), regs->cntr);
+ I915_WRITE(DVSSURF(pipe), regs->surf);
+}
+
+static void
+ilk_update_plane(struct drm_plane *plane,
+ struct drm_framebuffer *fb,
+ const struct intel_plane_coords *coords)
+{
+ struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ int pipe = intel_plane->pipe;
+
+ ilk_calc_plane(plane, fb, coords);
+ ilk_prepare_plane(plane);
+ ilk_commit_plane(plane);
POSTING_READ(DVSSURF(pipe));
}
@@ -464,21 +553,34 @@ ilk_disable_plane(struct drm_plane *plane)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane);
int pipe = intel_plane->pipe;
+ struct intel_plane_regs *regs = &intel_plane->regs;
- I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
+ regs->cntr &= ~DVS_ENABLE;
/* Disable the scaler */
- I915_WRITE(DVSSCALE(pipe), 0);
- /* Flush double buffered register updates */
- I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
+ regs->scale = 0;
+ ilk_commit_plane(plane);
POSTING_READ(DVSSURF(pipe));
}
+void intel_calc_sprite(struct drm_plane *plane,
+ struct drm_framebuffer *fb,
+ const struct intel_plane_coords *coords)
+{
+ struct drm_device *dev = plane->dev;
+
+ if (INTEL_INFO(dev)->gen >= 7)
+ ivb_calc_plane(plane, fb, coords);
+ else
+ ilk_calc_plane(plane, fb, coords);
+}
+
static void
intel_enable_primary(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_plane_regs *regs = &intel_crtc->primary_regs;
int reg = DSPCNTR(intel_crtc->plane);
if (!intel_crtc->primary_disabled)
@@ -487,7 +589,8 @@ intel_enable_primary(struct drm_crtc *crtc)
intel_crtc->primary_disabled = false;
intel_update_fbc(dev);
- I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
+ regs->cntr = I915_READ(reg) | DISPLAY_PLANE_ENABLE;
+ dev_priv->display.commit_plane(crtc);
}
static void
@@ -496,12 +599,14 @@ intel_disable_primary(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_plane_regs *regs = &intel_crtc->primary_regs;
int reg = DSPCNTR(intel_crtc->plane);
if (intel_crtc->primary_disabled)
return;
- I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
+ regs->cntr = I915_READ(reg) & ~DISPLAY_PLANE_ENABLE;
+ dev_priv->display.commit_plane(crtc);
intel_crtc->primary_disabled = true;
intel_update_fbc(dev);
@@ -513,49 +618,39 @@ ilk_update_colorkey(struct drm_plane *plane,
{
struct drm_device *dev = plane->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_plane *intel_plane;
- u32 dvscntr;
- int ret = 0;
-
- intel_plane = to_intel_plane(plane);
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ struct intel_plane_regs *regs = &intel_plane->regs;
- I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
- I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
- I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
+ regs->keyval = key->min_value;
+ regs->keymaxval = key->max_value;
+ regs->keymsk = key->channel_mask;
- dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
- dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
+ regs->cntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
if (key->flags & I915_SET_COLORKEY_DESTINATION)
- dvscntr |= DVS_DEST_KEY;
+ regs->cntr |= DVS_DEST_KEY;
else if (key->flags & I915_SET_COLORKEY_SOURCE)
- dvscntr |= DVS_SOURCE_KEY;
- I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
+ regs->cntr |= DVS_SOURCE_KEY;
+ ilk_commit_plane(plane);
POSTING_READ(DVSKEYMSK(intel_plane->pipe));
- return ret;
+ return 0;
}
static void
ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
{
- struct drm_device *dev = plane->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_plane *intel_plane;
- u32 dvscntr;
-
- intel_plane = to_intel_plane(plane);
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ const struct intel_plane_regs *regs = &intel_plane->regs;
- key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
- key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
- key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
+ key->min_value = regs->keyval;
+ key->max_value = regs->keymaxval;
+ key->channel_mask = regs->keymsk;
key->flags = 0;
- dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
-
- if (dvscntr & DVS_DEST_KEY)
+ if (regs->cntr & DVS_DEST_KEY)
key->flags = I915_SET_COLORKEY_DESTINATION;
- else if (dvscntr & DVS_SOURCE_KEY)
+ else if (regs->cntr & DVS_SOURCE_KEY)
key->flags = I915_SET_COLORKEY_SOURCE;
else
key->flags = I915_SET_COLORKEY_NONE;
@@ -793,6 +888,7 @@ static uint32_t snb_plane_formats[] = {
int
intel_plane_init(struct drm_device *dev, enum pipe pipe)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane;
unsigned long possible_crtcs;
const uint32_t *plane_formats;
@@ -815,6 +911,13 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
intel_plane->update_colorkey = ilk_update_colorkey;
intel_plane->get_colorkey = ilk_get_colorkey;
+ intel_plane->calc = ilk_calc_plane;
+ intel_plane->prepare = ilk_prepare_plane;
+ intel_plane->commit = ilk_commit_plane;
+
+ intel_plane->regs.cntr = I915_READ(DVSCNTR(pipe));
+ intel_plane->regs.surf = I915_READ(DVSSURF(pipe));
+
if (IS_GEN6(dev)) {
plane_formats = snb_plane_formats;
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
@@ -831,6 +934,13 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
intel_plane->update_colorkey = ivb_update_colorkey;
intel_plane->get_colorkey = ivb_get_colorkey;
+ intel_plane->calc = ivb_calc_plane;
+ intel_plane->prepare = ivb_prepare_plane;
+ intel_plane->commit = ivb_commit_plane;
+
+ intel_plane->regs.cntr = I915_READ(SPRCTL(pipe));
+ intel_plane->regs.surf = I915_READ(SPRSURF(pipe));
+
plane_formats = snb_plane_formats;
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
break;
--
1.7.8.6
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next prev parent reply other threads:[~2012-10-25 18:18 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-25 18:05 [PATCH 00/51] Atomic mode setting and page flip ville.syrjala
2012-10-25 18:05 ` [PATCH 01/51] drm: Be more paranoid with integer overflows ville.syrjala
2012-10-25 18:05 ` [PATCH 02/51] drm: Constify some function arguments ville.syrjala
2012-10-25 18:05 ` [PATCH 03/51] drm: Ignore blob propertys in drm_property_change_is_valid() ville.syrjala
2012-10-25 18:05 ` [PATCH 04/51] drm: Add struct drm_region and assorted utility functions ville.syrjala
2012-10-25 18:05 ` [PATCH 05/51] drm: Add drm_calc_{hscale, vscale}() " ville.syrjala
2012-10-25 18:05 ` [PATCH 06/51] drm: Keep a copy of last plane coordinates ville.syrjala
2012-10-25 18:05 ` [PATCH 07/51] drm: Add restore_fbdev_mode() hook to drm_fb_helper ville.syrjala
2012-10-25 18:05 ` [PATCH 08/51] drm: Export drm_property_create_blob() and drm_property_destroy_blob() ville.syrjala
2012-10-25 18:05 ` [PATCH 09/51] drm: Allow signed values for range properties ville.syrjala
2012-10-25 18:05 ` [PATCH 10/51] drm: Allow drm_mode_object_find() to look up an object of any type ville.syrjala
2012-10-25 18:05 ` [PATCH 11/51] drm: Export drm_encoder_crtc_ok ville.syrjala
2012-10-25 18:05 ` [PATCH 12/51] drm: Export drm_crtc_prepare_encoders() ville.syrjala
2012-10-25 18:05 ` [PATCH 13/51] drm: Refactor object property check code ville.syrjala
2012-10-25 18:05 ` [PATCH 14/51] drm: Export mode<->umode conversion functions ville.syrjala
2012-10-25 18:05 ` [PATCH 15/51] drm: Make blobs resizeable ville.syrjala
2012-10-25 18:05 ` [PATCH 16/51] drm: Add drm_flip helper ville.syrjala
2012-10-25 18:05 ` [PATCH 17/51] drm: Add mode_blob and connector_ids_blob to drm_crtc ville.syrjala
2012-10-25 18:05 ` [PATCH 18/51] drm: Add the atomic modeset ioctl ville.syrjala
2012-10-25 18:05 ` [PATCH 19/51] drm/i915: Fix display pixel format handling ville.syrjala
2012-10-25 18:05 ` [PATCH 20/51] drm/i915: Add SURFLIVE register definitions ville.syrjala
2012-10-25 18:05 ` [PATCH 21/51] drm/i915: Implement execbuffer wait for all planes ville.syrjala
2012-10-25 18:05 ` [PATCH 22/51] drm/i915: Check framebuffer stride more thoroughly ville.syrjala
2012-10-25 18:05 ` [PATCH 23/51] drm/i915: Check the framebuffer offset ville.syrjala
2012-10-25 18:05 ` [PATCH 24/51] drm/i915: Handle framebuffer offsets[] ville.syrjala
2012-10-25 18:05 ` [PATCH 25/51] drm/i915: Implement proper clipping for video sprites ville.syrjala
2012-10-25 18:05 ` [PATCH 26/51] drm/i915: pixel_size == cpp ville.syrjala
2012-10-25 18:05 ` [PATCH 27/51] drm/i915: Bad pixel formats can't reach the sprite code ville.syrjala
2012-10-25 18:05 ` [PATCH 28/51] drm/i915: Implement restore_fbdev_mode hook ville.syrjala
2012-10-25 18:05 ` [PATCH 29/51] drm/i915: Split clipping and checking from update_plane hook ville.syrjala
2012-10-25 18:05 ` [PATCH 30/51] drm/i915: Factor out i9xx_compute_clocks() like ironlake_compute_clocks() ville.syrjala
2012-10-25 18:05 ` [PATCH 31/51] drm/i915: Consitify adjusted_mode parameter ville.syrjala
2012-10-25 18:05 ` [PATCH 32/51] drm/i915: Add intel_check_clock() ville.syrjala
2012-10-25 18:05 ` [PATCH 33/51] drm/i915: store cursor_handle in struct intel_crtc ville.syrjala
2012-10-25 18:05 ` [PATCH 34/51] drm/i915: split cursor setting code into prepare/commit/unref parts ville.syrjala
2012-10-25 18:05 ` [PATCH 35/51] drm/i915: unstatic cursor functions for use with atomic modesetting ville.syrjala
2012-10-25 18:05 ` [PATCH 36/51] drm/i915: Unstatic intel_finish_fb() ville.syrjala
2012-10-25 18:05 ` [PATCH 37/51] drm/i915: Pull intel_pipe_set_base() out of the crtc_mode_set() functions ville.syrjala
2012-10-25 18:05 ` [PATCH 38/51] drm/i915: Unstatic intel_crtc_update_sarea() ville.syrjala
2012-10-25 18:05 ` [PATCH 39/51] drm/i915: Introduce intel_crtc_update_sarea_pos() ville.syrjala
2012-10-25 18:05 ` [PATCH 40/51] drm/i915: Constify mode argument to intel_modeset_adjusted_mode() ville.syrjala
2012-10-25 18:05 ` [PATCH 41/51] drm/i915: Unstatic intel_crtc_mode_fixup() ville.syrjala
2012-10-25 18:05 ` [PATCH 42/51] drm/i915: Introduce intel_plane_regs ville.syrjala
2012-10-25 18:05 ` [PATCH 43/51] drm/i915: Split primary plane update_plane() into calc+commit phases ville.syrjala
2012-10-25 18:05 ` ville.syrjala [this message]
2012-10-25 18:05 ` [PATCH 45/51] drm/i915: Implement atomic modesetting ville.syrjala
2012-10-25 18:05 ` [PATCH 46/51] drm/i915: Add support for atomic modesetting completion events ville.syrjala
2012-11-01 11:12 ` Daniel Vetter
2012-11-01 14:39 ` Jesse Barnes
2012-11-01 17:07 ` Ville Syrjälä
2012-11-01 17:12 ` Jesse Barnes
2012-11-01 22:39 ` Daniel Vetter
2012-11-02 9:10 ` Ville Syrjälä
2012-11-07 20:29 ` Rob Clark
2012-11-09 21:20 ` Daniel Vetter
2012-11-09 21:25 ` Rob Clark
2012-10-25 18:05 ` [PATCH 47/51] drm/i915: Add atomic page flip support ville.syrjala
2012-10-25 18:05 ` [PATCH 48/51] drm/i915: Unstatic intel_enable_primary() and intel_disable_primary() ville.syrjala
2012-10-25 18:05 ` [PATCH 49/51] drm/i915: Respect primary_disabled in crtc_enable() ville.syrjala
2012-10-25 18:05 ` [PATCH 50/51] drm/i915: Enable/disable primary plane in calc_plane() ville.syrjala
2012-10-25 18:05 ` [PATCH 51/51] drm/i915: Add primary plane disable logic to atomic mode setting code ville.syrjala
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