From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 5/9] drm/i915: Include display_mmio_offset in sequencer index/data registers
Date: Fri, 25 Jan 2013 21:44:45 +0200 [thread overview]
Message-ID: <1359143089-14284-6-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1359143089-14284-1-git-send-email-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
SR01 needs to be touched to disable VGA on non-UMS setups too.
So the sequencer registers need to include the appripriate offset
on VLV.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 213ff6c..9f4305f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -141,9 +141,15 @@
#define VGA_MSR_MEM_EN (1<<1)
#define VGA_MSR_CGA_MODE (1<<0)
-#define VGA_SR_INDEX 0x3c4
+/*
+ * SR01 is the only VGA register touched on non-UMS setups.
+ * VLV doesn't do UMS, so the sequencer index/data registers
+ * are the only VGA registers which need to include
+ * display_mmio_offset.
+ */
+#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
#define SR01 1
-#define VGA_SR_DATA 0x3c5
+#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
#define VGA_AR_INDEX 0x3c0
#define VGA_AR_VID_EN (1<<5)
--
1.7.12.4
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next prev parent reply other threads:[~2013-01-25 19:45 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-25 19:44 [PATCH 0/9] drm/915: Get rid of IS_DISPLAYREG(), continued ville.syrjala
2013-01-25 19:44 ` [PATCH v2 1/9] drm/i915: PLL registers need an offset on VLV ville.syrjala
2013-01-25 19:44 ` [PATCH 2/9] drm/i915: Always use adpa_reg ville.syrjala
2013-01-25 19:44 ` [PATCH 3/9] drm/i915: VLV doesn't have SDVO ville.syrjala
2013-01-25 19:44 ` [PATCH v2 4/9] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLV ville.syrjala
2013-01-25 19:44 ` ville.syrjala [this message]
2013-01-26 16:43 ` [PATCH 5/9] drm/i915: Include display_mmio_offset in sequencer index/data registers Daniel Vetter
2013-01-25 19:44 ` [PATCH 6/9] drm/i915: Introduce i915_vgacntrl_reg() ville.syrjala
2013-01-25 19:44 ` [PATCH 7/9] drm/i915: Kill IS_DISPLAYREG() ville.syrjala
2013-01-25 19:44 ` [PATCH 8/9] drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() too ville.syrjala
2013-01-31 10:24 ` Daniel Vetter
2013-01-25 19:44 ` [PATCH 9/9] drm/i915: Don't touch VGA0/VGA1/VGA_PD on ILK+ ville.syrjala
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