From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: DRI Development <dri-devel@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: [PATCH 25/39] drm/radeon: s/drm_order/order_base_2/
Date: Wed, 10 Jul 2013 14:11:59 +0200 [thread overview]
Message-ID: <1373458333-5988-26-git-send-email-daniel.vetter@ffwll.ch> (raw)
In-Reply-To: <1373458333-5988-1-git-send-email-daniel.vetter@ffwll.ch>
Last driver and pretty obviously a major user of this little function.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/radeon/cik.c | 14 +++++++-------
drivers/gpu/drm/radeon/evergreen.c | 4 ++--
drivers/gpu/drm/radeon/ni.c | 6 +++---
drivers/gpu/drm/radeon/r100.c | 2 +-
drivers/gpu/drm/radeon/r600.c | 14 +++++++-------
drivers/gpu/drm/radeon/r600_cp.c | 6 +++---
drivers/gpu/drm/radeon/radeon_cp.c | 6 +++---
drivers/gpu/drm/radeon/si.c | 14 +++++++-------
8 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index ed1d910..1a8aa89 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2546,8 +2546,8 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
/* ring 0 - compute and gfx */
/* Set ring buffer size */
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
- rb_bufsz = drm_order(ring->ring_size / 8);
- tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
+ rb_bufsz = order_base_2(ring->ring_size / 8);
+ tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN
tmp |= BUF_SWAP_32BIT;
#endif
@@ -2926,7 +2926,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
tmp = RREG32(CP_HPD_EOP_CONTROL);
tmp &= ~EOP_SIZE_MASK;
- tmp |= drm_order(MEC_HPD_SIZE / 8);
+ tmp |= order_base_2(MEC_HPD_SIZE / 8);
WREG32(CP_HPD_EOP_CONTROL, tmp);
}
cik_srbm_select(rdev, 0, 0, 0, 0);
@@ -3041,9 +3041,9 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
~(QUEUE_SIZE_MASK | RPTR_BLOCK_SIZE_MASK);
mqd->queue_state.cp_hqd_pq_control |=
- drm_order(rdev->ring[idx].ring_size / 8);
+ order_base_2(rdev->ring[idx].ring_size / 8);
mqd->queue_state.cp_hqd_pq_control |=
- (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8);
+ (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8);
#ifdef __BIG_ENDIAN
mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
#endif
@@ -3386,7 +3386,7 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev)
WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
/* Set ring buffer size in dwords */
- rb_bufsz = drm_order(ring->ring_size / 4);
+ rb_bufsz = order_base_2(ring->ring_size / 4);
rb_cntl = rb_bufsz << 1;
#ifdef __BIG_ENDIAN
rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
@@ -5018,7 +5018,7 @@ static int cik_irq_init(struct radeon_device *rdev)
WREG32(INTERRUPT_CNTL, interrupt_cntl);
WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
- rb_bufsz = drm_order(rdev->ih.ring_size / 4);
+ rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
IH_WPTR_OVERFLOW_CLEAR |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e49059d..b4b5620 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2879,8 +2879,8 @@ static int evergreen_cp_resume(struct radeon_device *rdev)
RREG32(GRBM_SOFT_RESET);
/* Set ring buffer size */
- rb_bufsz = drm_order(ring->ring_size / 8);
- tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
+ rb_bufsz = order_base_2(ring->ring_size / 8);
+ tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN
tmp |= BUF_SWAP_32BIT;
#endif
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index f30127c..fd9a583 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1571,8 +1571,8 @@ static int cayman_cp_resume(struct radeon_device *rdev)
/* Set ring buffer size */
ring = &rdev->ring[ridx[i]];
- rb_cntl = drm_order(ring->ring_size / 8);
- rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
+ rb_cntl = order_base_2(ring->ring_size / 8);
+ rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
#ifdef __BIG_ENDIAN
rb_cntl |= BUF_SWAP_32BIT;
#endif
@@ -1731,7 +1731,7 @@ int cayman_dma_resume(struct radeon_device *rdev)
WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
/* Set ring buffer size in dwords */
- rb_bufsz = drm_order(ring->ring_size / 4);
+ rb_bufsz = order_base_2(ring->ring_size / 4);
rb_cntl = rb_bufsz << 1;
#ifdef __BIG_ENDIAN
rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index c9affef..b0b2640 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1106,7 +1106,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
}
/* Align ring size */
- rb_bufsz = drm_order(ring_size / 8);
+ rb_bufsz = order_base_2(ring_size / 8);
ring_size = (1 << (rb_bufsz + 1)) * 4;
r100_cp_load_microcode(rdev);
r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 2d3655f..aea76eb 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2424,8 +2424,8 @@ int r600_cp_resume(struct radeon_device *rdev)
WREG32(GRBM_SOFT_RESET, 0);
/* Set ring buffer size */
- rb_bufsz = drm_order(ring->ring_size / 8);
- tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
+ rb_bufsz = order_base_2(ring->ring_size / 8);
+ tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN
tmp |= BUF_SWAP_32BIT;
#endif
@@ -2478,7 +2478,7 @@ void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsign
int r;
/* Align ring size */
- rb_bufsz = drm_order(ring_size / 8);
+ rb_bufsz = order_base_2(ring_size / 8);
ring_size = (1 << (rb_bufsz + 1)) * 4;
ring->ring_size = ring_size;
ring->align_mask = 16 - 1;
@@ -2558,7 +2558,7 @@ int r600_dma_resume(struct radeon_device *rdev)
WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
/* Set ring buffer size in dwords */
- rb_bufsz = drm_order(ring->ring_size / 4);
+ rb_bufsz = order_base_2(ring->ring_size / 4);
rb_cntl = rb_bufsz << 1;
#ifdef __BIG_ENDIAN
rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
@@ -2667,7 +2667,7 @@ int r600_uvd_rbc_start(struct radeon_device *rdev)
WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
/* Set ring buffer size */
- rb_bufsz = drm_order(ring->ring_size);
+ rb_bufsz = order_base_2(ring->ring_size);
rb_bufsz = (0x1 << 8) | rb_bufsz;
WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
@@ -3742,7 +3742,7 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
u32 rb_bufsz;
/* Align ring size */
- rb_bufsz = drm_order(ring_size / 4);
+ rb_bufsz = order_base_2(ring_size / 4);
ring_size = (1 << rb_bufsz) * 4;
rdev->ih.ring_size = ring_size;
rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
@@ -3979,7 +3979,7 @@ int r600_irq_init(struct radeon_device *rdev)
WREG32(INTERRUPT_CNTL, interrupt_cntl);
WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
- rb_bufsz = drm_order(rdev->ih.ring_size / 4);
+ rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
IH_WPTR_OVERFLOW_CLEAR |
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 1c51c08..d8eb48b 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -2200,13 +2200,13 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
+ init->ring_size / sizeof(u32));
dev_priv->ring.size = init->ring_size;
- dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
+ dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
- dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
+ dev_priv->ring.rptr_update_l2qw = order_base_2(/* init->rptr_update */ 4096 / 8);
dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
- dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
+ dev_priv->ring.fetch_size_l2ow = order_base_2(/* init->fetch_size */ 32 / 16);
dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index efc4f64..3cae2bb 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -1444,13 +1444,13 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
+ init->ring_size / sizeof(u32));
dev_priv->ring.size = init->ring_size;
- dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
+ dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
- dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
+ dev_priv->ring.rptr_update_l2qw = order_base_2( /* init->rptr_update */ 4096 / 8);
dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
- dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
+ dev_priv->ring.fetch_size_l2ow = order_base_2( /* init->fetch_size */ 32 / 16);
dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 2349067..9361c3e 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3394,8 +3394,8 @@ static int si_cp_resume(struct radeon_device *rdev)
/* ring 0 - compute and gfx */
/* Set ring buffer size */
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
- rb_bufsz = drm_order(ring->ring_size / 8);
- tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
+ rb_bufsz = order_base_2(ring->ring_size / 8);
+ tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN
tmp |= BUF_SWAP_32BIT;
#endif
@@ -3427,8 +3427,8 @@ static int si_cp_resume(struct radeon_device *rdev)
/* ring1 - compute only */
/* Set ring buffer size */
ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
- rb_bufsz = drm_order(ring->ring_size / 8);
- tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
+ rb_bufsz = order_base_2(ring->ring_size / 8);
+ tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN
tmp |= BUF_SWAP_32BIT;
#endif
@@ -3453,8 +3453,8 @@ static int si_cp_resume(struct radeon_device *rdev)
/* ring2 - compute only */
/* Set ring buffer size */
ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
- rb_bufsz = drm_order(ring->ring_size / 8);
- tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
+ rb_bufsz = order_base_2(ring->ring_size / 8);
+ tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN
tmp |= BUF_SWAP_32BIT;
#endif
@@ -5398,7 +5398,7 @@ static int si_irq_init(struct radeon_device *rdev)
WREG32(INTERRUPT_CNTL, interrupt_cntl);
WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
- rb_bufsz = drm_order(rdev->ih.ring_size / 4);
+ rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
IH_WPTR_OVERFLOW_CLEAR |
--
1.8.3.2
next prev parent reply other threads:[~2013-07-10 12:12 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-10 12:11 [PATCH 00/39] clean out drm cruft and hide it better for kms drivers Daniel Vetter
2013-07-10 12:11 ` [PATCH 01/39] drm: remove drm_modctx ioctl and use drm_noop instead Daniel Vetter
2013-07-10 12:11 ` [PATCH 02/39] drm: kill dev->context_wait Daniel Vetter
2013-07-10 12:11 ` [PATCH 03/39] drm: remove dev->last_switch Daniel Vetter
2013-07-10 12:11 ` [PATCH 04/39] drm: kill dev->interrupt_flag and dev->dma_flag Daniel Vetter
2013-07-10 12:11 ` [PATCH 05/39] drm: kill dev->ctx_start and dev->lck_start Daniel Vetter
2013-07-10 12:11 ` [PATCH 06/39] drm/radoen: kill radeon_dma_ioctl_kms Daniel Vetter
2013-07-10 12:11 ` [PATCH 07/39] drm: kill dev->buf_readers and dev->buf_writers Daniel Vetter
2013-07-10 12:11 ` [PATCH 08/39] drm: remove redundant clears from drm_setup Daniel Vetter
2013-07-10 13:28 ` David Herrmann
2013-07-10 15:19 ` Daniel Vetter
2013-07-10 12:11 ` [PATCH 09/39] drm/omap: kill firstopen callback Daniel Vetter
2013-07-10 12:11 ` [PATCH 10/39] drm/radeon: kill firstopen callback for kms driver Daniel Vetter
2013-07-10 12:11 ` [PATCH 11/39] drm/imx: kill firstopen callback Daniel Vetter
2013-07-10 12:11 ` [PATCH 12/39] drm/vmwgfx: remove ->firstopen callback Daniel Vetter
2013-07-10 12:11 ` [PATCH 13/39] drm: don't call ->firstopen for KMS drivers Daniel Vetter
2013-07-10 18:17 ` [PATCH] " Daniel Vetter
2013-07-11 7:54 ` Laurent Pinchart
2013-07-11 10:19 ` Daniel Vetter
2013-07-13 14:43 ` Daniel Vetter
2013-07-13 14:45 ` Daniel Vetter
2013-07-22 9:02 ` Laurent Pinchart
2013-07-10 12:11 ` [PATCH 14/39] drm: kill dev->driver->set_version Daniel Vetter
2013-07-10 12:11 ` [PATCH 15/39] drm/radeon: remove DRIVER_HAS_DMA/SG/PCI_DMA from the kms driver Daniel Vetter
2013-07-10 12:11 ` [PATCH 16/39] drm: fold in drm_sg_alloc into the ioctl Daniel Vetter
2013-07-10 12:11 ` [PATCH 17/39] drm: hide legacy sg cleanup better from common code Daniel Vetter
2013-07-10 12:11 ` [PATCH 18/39] drm: disallow legacy sg ioctls for modesetting drivers Daniel Vetter
2013-07-10 12:11 ` [PATCH 19/39] drm: mark dma setup/teardown as legacy systems Daniel Vetter
2013-07-10 12:11 ` [PATCH 20/39] drm/nouveau: drop DRIVER_PCI_DMA and DRIVER_SG Daniel Vetter
2013-07-10 12:11 ` [PATCH 21/39] drm: disallow legacy dma ioctls for modesetting drivers Daniel Vetter
2013-07-10 12:11 ` [PATCH 22/39] drm: move drm_getsarea into drm_bufs.c Daniel Vetter
2013-07-10 12:11 ` [PATCH 23/39] drm/bufs: s/drm_order/order_base_2/ Daniel Vetter
2013-07-10 12:11 ` [PATCH 24/39] drm/r128: s/drm_order/order_base_2/ Daniel Vetter
2013-07-10 12:11 ` Daniel Vetter [this message]
2013-07-10 12:12 ` [PATCH 26/39] drm: remove drm_order Daniel Vetter
2013-07-10 12:12 ` [PATCH 27/39] drm: mark context support as a legacy subsystem Daniel Vetter
2013-07-10 12:12 ` [PATCH 28/39] drm/vmwgfx: remove redundant clearing of driver->dma_quiescent Daniel Vetter
2013-07-10 12:12 ` [PATCH 29/39] drm: remove FASYNC support Daniel Vetter
2013-07-10 14:57 ` [PATCH] " Daniel Vetter
2013-07-10 15:24 ` Daniel Vetter
2013-07-10 15:25 ` Daniel Vetter
2013-07-11 0:26 ` Laurent Pinchart
2013-07-10 12:12 ` [PATCH 30/39] drm: rip out DRIVER_FB_DMA and related code Daniel Vetter
2013-07-10 12:12 ` [PATCH 31/39] drm: rip out a few unused DRIVER flags Daniel Vetter
2013-07-10 12:12 ` [PATCH 32/39] drm: remove a bunch of unused #defines from drmP.h Daniel Vetter
2013-07-10 12:12 ` [PATCH 33/39] drm: rip out drm_core_has_MTRR checks Daniel Vetter
2013-07-10 13:51 ` David Herrmann
2013-07-10 15:22 ` Daniel Vetter
2013-07-10 15:41 ` David Herrmann
2013-07-10 15:59 ` Daniel Vetter
2013-07-10 16:13 ` [PATCH 1/2] " Daniel Vetter
2013-07-10 16:13 ` [PATCH 2/2] drm/docs: rip out removed driver flags documentation Daniel Vetter
2013-07-10 16:27 ` [PATCH 33/39] drm: rip out drm_core_has_MTRR checks Andy Lutomirski
2013-07-10 16:41 ` Daniel Vetter
2013-07-10 12:12 ` [PATCH 34/39] drm: remove the dma_ioctl special-case Daniel Vetter
2013-07-10 14:34 ` David Herrmann
2013-07-10 14:59 ` [PATCH] " Daniel Vetter
2013-07-10 12:12 ` [PATCH 35/39] drm/memory: don't export agp helpers Daniel Vetter
2013-07-10 12:12 ` [PATCH 36/39] drm: hollow-out GET_CLIENT ioctl Daniel Vetter
2013-07-16 12:33 ` Daniel Vetter
2013-07-16 13:14 ` [PATCH] " Daniel Vetter
2013-07-16 13:30 ` Chris Wilson
2013-07-17 13:52 ` David Herrmann
2013-07-10 12:12 ` [PATCH 37/39] drm: no-op out GET_STATS ioctl Daniel Vetter
2013-07-10 12:12 ` [PATCH 38/39] drm: fix locking in gem debugfs/procfs file Daniel Vetter
2013-07-10 12:12 ` [PATCH 39/39] drm: remove procfs code, take 2 Daniel Vetter
2013-07-10 20:44 ` [PATCH] " Daniel Vetter
2013-07-10 15:32 ` [PATCH 00/39] clean out drm cruft and hide it better for kms drivers David Herrmann
2013-07-10 15:51 ` [PATCH 1/2] drm: rip out dev->last_checked Daniel Vetter
2013-07-10 15:51 ` [PATCH 2/2] drm: move dev data clearing from drm_setup to lastclose Daniel Vetter
2013-07-11 14:09 ` [PATCH 00/39] clean out drm cruft and hide it better for kms drivers Alex Deucher
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