From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 04/11] drm/i915: Add state readout and checking for has_dp_encoder and dp_m_n
Date: Fri, 6 Sep 2013 23:29:01 +0300 [thread overview]
Message-ID: <1378499348-4281-5-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1378499348-4281-1-git-send-email-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add functions to read out the CPU and PCH transcoder M/N values,
and use them to fill out the pipe config dp_m_n information. And
while at it populate has_dp_encoder too.
Also refactor ironlake_get_fdi_m_n_config() to simply call the new
intel_cpu_transcoder_get_m_n() function.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 76 +++++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dp.c | 4 ++
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 72 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 35ad910..3bfde06 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5862,20 +5862,64 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
return ret;
}
-static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
+static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum pipe pipe = crtc->pipe;
+
+ m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
+ m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
+ m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
+ & ~TU_SIZE_MASK;
+ m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
+ m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
+ & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+}
+
+static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
+ enum transcoder transcoder,
+ struct intel_link_m_n *m_n)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder transcoder = pipe_config->cpu_transcoder;
+ enum pipe pipe = crtc->pipe;
+
+ if (INTEL_INFO(dev)->gen >= 5) {
+ m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
+ m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
+ m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
+ & ~TU_SIZE_MASK;
+ m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
+ m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
+ & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ } else {
+ m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
+ m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
+ m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
+ & ~TU_SIZE_MASK;
+ m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
+ m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
+ & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ }
+}
+
+void intel_dp_get_m_n(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
+{
+ if (crtc->config.has_pch_encoder)
+ intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
+ else
+ intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
+ &pipe_config->dp_m_n);
+}
- pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
- pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
- pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
- & ~TU_SIZE_MASK;
- pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
- pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
- & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
+{
+ intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
+ &pipe_config->fdi_m_n);
}
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
@@ -8245,6 +8289,11 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
pipe_config->fdi_m_n.tu);
+ DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+ pipe_config->has_dp_encoder,
+ pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
+ pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
+ pipe_config->dp_m_n.tu);
DRM_DEBUG_KMS("requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->requested_mode);
DRM_DEBUG_KMS("adjusted mode:\n");
@@ -8614,6 +8663,13 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I(fdi_m_n.link_n);
PIPE_CONF_CHECK_I(fdi_m_n.tu);
+ PIPE_CONF_CHECK_I(has_dp_encoder);
+ PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
+ PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
+ PIPE_CONF_CHECK_I(dp_m_n.link_m);
+ PIPE_CONF_CHECK_I(dp_m_n.link_n);
+ PIPE_CONF_CHECK_I(dp_m_n.tu);
+
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c192dbb..be0449b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1399,6 +1399,10 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
pipe_config->adjusted_mode.flags |= flags;
+ pipe_config->has_dp_encoder = true;
+
+ intel_dp_get_m_n(crtc, pipe_config);
+
if (dp_to_dig_port(intel_dp)->port == PORT_A) {
if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
pipe_config->port_clock = 162000;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index dbf04be..a4e8689 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -801,5 +801,7 @@ extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
+extern void intel_dp_get_m_n(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config);
#endif /* __INTEL_DRV_H__ */
--
1.8.1.5
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next prev parent reply other threads:[~2013-09-06 20:29 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-06 20:28 [PATCH 00/11] drm/i915: adjusted_mode.clock vs. port_clock v3 ville.syrjala
2013-09-06 20:28 ` [PATCH 01/11] drm/i915: Don't factor in pixel multplier when deriving dotclock from link clock and M/N values ville.syrjala
2013-09-06 20:28 ` [PATCH v2 02/11] drm/i915: Make adjusted_mode.clock non-pixel multiplied ville.syrjala
2013-09-13 11:40 ` Jani Nikula
2013-09-06 20:29 ` [PATCH v2 03/11] drm/i915: Add support for pipe_bpp readout ville.syrjala
2013-09-13 11:59 ` Jani Nikula
2013-09-06 20:29 ` ville.syrjala [this message]
2013-09-10 14:02 ` [PATCH v2] drm/i915: Add state readout and checking for has_dp_encoder and dp_m_n ville.syrjala
2013-09-13 12:11 ` Jani Nikula
2013-09-06 20:29 ` [PATCH 05/11] drm/i915: Make intel_fuzzy_clock_check() take in arbitrary clocks ville.syrjala
2013-09-13 12:55 ` Daniel Vetter
2013-09-06 20:29 ` [PATCH 06/11] drm/i915: Add intel_dotclock_calculate() ville.syrjala
2013-09-13 12:30 ` Jani Nikula
2013-09-13 12:43 ` Ville Syrjälä
2013-09-13 12:59 ` [PATCH v2] " ville.syrjala
2013-09-16 11:14 ` Jani Nikula
2013-09-16 20:41 ` Daniel Vetter
2013-09-17 8:16 ` Ville Syrjälä
2013-09-06 20:29 ` [PATCH 07/11] drm/i915: Make i9xx_crtc_clock_get() use dpll_hw_state ville.syrjala
2013-09-13 12:40 ` Jani Nikula
2013-09-13 13:12 ` Ville Syrjälä
2013-09-13 13:18 ` [PATCH v2] " ville.syrjala
2013-09-13 13:44 ` Jani Nikula
2013-09-06 20:29 ` [PATCH 08/11] drm/i915: Make i9xx_crtc_clock_get() work for PCH DPLLs ville.syrjala
2013-09-08 12:35 ` Daniel Vetter
2013-09-09 11:06 ` [PATCH v2] " ville.syrjala
2013-09-13 13:04 ` Jani Nikula
2013-09-13 13:06 ` Ville Syrjälä
2013-09-13 13:47 ` Jani Nikula
2013-09-13 13:54 ` Ville Syrjälä
2013-09-16 20:43 ` Daniel Vetter
2013-09-06 20:29 ` [PATCH 09/11] drm/i915: Fix port_clock and adjusted_mode.clock readout all over ville.syrjala
2013-09-08 12:37 ` Daniel Vetter
2013-09-09 10:35 ` [PATCH v2] " ville.syrjala
2013-09-09 11:34 ` [PATCH v3] " ville.syrjala
2013-09-13 13:00 ` [PATCH v4] " ville.syrjala
2013-09-16 11:16 ` Jani Nikula
2013-09-06 20:29 ` [PATCH v2 10/11] drm/i915: Add PIPE_CONF_CHECK_CLOCK_FUZZY() ville.syrjala
2013-09-06 20:29 ` [PATCH v2 11/11] drm/i915: Add fuzzy clock check for port_clock ville.syrjala
2013-09-16 21:16 ` Daniel Vetter
2013-09-08 12:38 ` [PATCH 00/11] drm/i915: adjusted_mode.clock vs. port_clock v3 Daniel Vetter
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