From: Alexandre Macabies <web+oss@zopieux.com>
To: linux-wpan@vger.kernel.org
Cc: Alexandre Macabies <web+oss@zopieux.com>,
Alexander Aring <aar@pengutronix.de>
Subject: [PATCH v2 3/3] mrf24j40: apply the security-enabled bit on secured outbound frames
Date: Mon, 14 Mar 2016 21:46:14 +0100 [thread overview]
Message-ID: <1457988374-31220-3-git-send-email-web+oss@zopieux.com> (raw)
In-Reply-To: <1457988374-31220-1-git-send-email-web+oss@zopieux.com>
We set the TXNSECEN bit of register TXNCON to on when transmitting a
security-enabled frame, as described in section 3.12.2 of the MRF
datasheet.
Signed-off-by: Alexander Aring <aar@pengutronix.de>
Signed-off-by: Alexandre Macabies <web+oss@zopieux.com>
Reviewed-by: Stefan Schmidt <stefan@osg.samsung.com>
---
drivers/net/ieee802154/mrf24j40.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ieee802154/mrf24j40.c b/drivers/net/ieee802154/mrf24j40.c
index adc67be..f446db8 100644
--- a/drivers/net/ieee802154/mrf24j40.c
+++ b/drivers/net/ieee802154/mrf24j40.c
@@ -61,6 +61,7 @@
#define REG_TXBCON0 0x1A
#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
#define BIT_TXNTRIG BIT(0)
+#define BIT_TXNSECEN BIT(1)
#define BIT_TXNACKREQ BIT(2)
#define REG_TXG1CON 0x1C
@@ -551,6 +552,9 @@ static void write_tx_buf_complete(void *context)
u8 val = BIT_TXNTRIG;
int ret;
+ if (ieee802154_is_secen(fc))
+ val |= BIT_TXNSECEN;
+
if (ieee802154_is_ackreq(fc))
val |= BIT_TXNACKREQ;
--
2.7.3
next prev parent reply other threads:[~2016-03-14 20:47 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-10 18:14 [PATCH 1/3] ieee802154: add security bit check function web+oss
2016-03-10 18:14 ` [PATCH 2/3] mrf24j40: fix security-enabled processing on inbound frames web+oss
2016-03-14 11:05 ` Stefan Schmidt
2016-03-10 18:14 ` [PATCH 3/3] mrf24j40: apply the security-enabled bit on secured outbound frames web+oss
2016-03-14 11:06 ` Stefan Schmidt
2016-03-14 11:03 ` [PATCH 1/3] ieee802154: add security bit check function Stefan Schmidt
2016-04-08 17:37 ` Marcel Holtmann
2016-03-14 20:46 ` [PATCH v2 " Alexandre Macabies
2016-03-14 20:46 ` [PATCH v2 2/3] mrf24j40: fix security-enabled processing on inbound frames Alexandre Macabies
2016-03-30 8:45 ` Stefan Schmidt
2016-03-14 20:46 ` Alexandre Macabies [this message]
2016-03-30 8:45 ` [PATCH v2 3/3] mrf24j40: apply the security-enabled bit on secured outbound frames Stefan Schmidt
2016-03-30 8:45 ` [PATCH v2 1/3] ieee802154: add security bit check function Stefan Schmidt
2016-03-30 14:05 ` Alan Ott
2016-03-30 16:43 ` Stefan Schmidt
2016-04-08 17:35 ` Marcel Holtmann
2016-04-12 16:53 ` [PATCH v3 " Alexandre Macabies
2016-04-12 16:53 ` [PATCH v3 2/3] mrf24j40: fix security-enabled processing on inbound frames Alexandre Macabies
2016-04-13 8:44 ` Marcel Holtmann
2016-04-12 16:53 ` [PATCH v3 3/3] mrf24j40: apply the security-enabled bit on secured outbound frames Alexandre Macabies
2016-04-13 8:44 ` Marcel Holtmann
2016-04-13 8:44 ` [PATCH v3 1/3] ieee802154: add security bit check function Marcel Holtmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1457988374-31220-3-git-send-email-web+oss@zopieux.com \
--to=web+oss@zopieux.com \
--cc=aar@pengutronix.de \
--cc=linux-wpan@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.