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From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net, schwab@linux-m68k.org, gerg@uclinux.org,
	agraf@suse.de, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs
Date: Wed,  4 May 2016 23:08:36 +0200	[thread overview]
Message-ID: <1462396135-20925-1-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1462392752-17703-1-git-send-email-laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 linux-user/main.c       |   7 ++
 target-m68k/cpu.h       |   4 -
 target-m68k/helper.h    |   2 -
 target-m68k/op_helper.c |  49 ------------
 target-m68k/qregs.def   |   2 -
 target-m68k/translate.c | 198 +++++++++++++++++++++++++++++++++++++++---------
 6 files changed, 169 insertions(+), 93 deletions(-)

diff --git a/linux-user/main.c b/linux-user/main.c
index 5f3ec97..74b02c7 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3034,6 +3034,13 @@ void cpu_loop(CPUM68KState *env)
             info._sifields._sigfault._addr = env->pc;
             queue_signal(env, info.si_signo, &info);
             break;
+        case EXCP_DIV0:
+            info.si_signo = TARGET_SIGFPE;
+            info.si_errno = 0;
+            info.si_code = TARGET_FPE_INTDIV;
+            info._sifields._sigfault._addr = env->pc;
+            queue_signal(env, info.si_signo, &info);
+            break;
         case EXCP_TRAP0:
             {
                 ts->sim_syscalls = 0;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 9415d2b..b300a92 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -94,10 +94,6 @@ typedef struct CPUM68KState {
     uint32_t macsr;
     uint32_t mac_mask;
 
-    /* Temporary storage for DIV helpers.  */
-    uint32_t div1;
-    uint32_t div2;
-
     /* MMU status.  */
     struct {
         uint32_t ar;
diff --git a/target-m68k/helper.h b/target-m68k/helper.h
index 0b819cb..80ee4f8 100644
--- a/target-m68k/helper.h
+++ b/target-m68k/helper.h
@@ -2,8 +2,6 @@ DEF_HELPER_1(bitrev, i32, i32)
 DEF_HELPER_1(ff1, i32, i32)
 DEF_HELPER_2(bfffo, i32, i32, i32)
 DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32)
-DEF_HELPER_2(divu, void, env, i32)
-DEF_HELPER_2(divs, void, env, i32)
 DEF_HELPER_2(set_sr, void, env, i32)
 DEF_HELPER_3(movec, void, env, i32, i32)
 
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 71caba9..bf3c813 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -245,52 +245,3 @@ void HELPER(bitfield_store)(CPUM68KState *env, uint32_t addr, uint32_t offset,
         break;
     }
 }
-
-void HELPER(divu)(CPUM68KState *env, uint32_t word)
-{
-    uint32_t num;
-    uint32_t den;
-    uint32_t quot;
-    uint32_t rem;
-
-    num = env->div1;
-    den = env->div2;
-    /* ??? This needs to make sure the throwing location is accurate.  */
-    if (den == 0) {
-        raise_exception(env, EXCP_DIV0);
-    }
-    quot = num / den;
-    rem = num % den;
-
-    env->cc_v = (word && quot > 0xffff ? -1 : 0);
-    env->cc_z = quot;
-    env->cc_n = quot;
-    env->cc_c = 0;
-
-    env->div1 = quot;
-    env->div2 = rem;
-}
-
-void HELPER(divs)(CPUM68KState *env, uint32_t word)
-{
-    int32_t num;
-    int32_t den;
-    int32_t quot;
-    int32_t rem;
-
-    num = env->div1;
-    den = env->div2;
-    if (den == 0) {
-        raise_exception(env, EXCP_DIV0);
-    }
-    quot = num / den;
-    rem = num % den;
-
-    env->cc_v = (word && quot != (int16_t)quot ? -1 : 0);
-    env->cc_z = quot;
-    env->cc_n = quot;
-    env->cc_c = 0;
-
-    env->div1 = quot;
-    env->div2 = rem;
-}
diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def
index 156c0f5..51ff43b 100644
--- a/target-m68k/qregs.def
+++ b/target-m68k/qregs.def
@@ -7,7 +7,5 @@ DEFO32(CC_C, cc_c)
 DEFO32(CC_N, cc_n)
 DEFO32(CC_V, cc_v)
 DEFO32(CC_Z, cc_z)
-DEFO32(DIV1, div1)
-DEFO32(DIV2, div2)
 DEFO32(MACSR, macsr)
 DEFO32(MAC_MASK, mac_mask)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 00fd2f1..b47f9c1 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1047,11 +1047,19 @@ static void gen_jmp(DisasContext *s, TCGv dest)
     s->is_jmp = DISAS_JUMP;
 }
 
+static inline void gen_raise_exception(int nr)
+{
+    TCGv_i32 tmp = tcg_const_i32(nr);
+
+    gen_helper_raise_exception(cpu_env, tmp);
+    tcg_temp_free_i32(tmp);
+}
+
 static void gen_exception(DisasContext *s, uint32_t where, int nr)
 {
     update_cc_op(s);
     gen_jmp_im(s, where);
-    gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
+    gen_raise_exception(nr);
 }
 
 static inline void gen_addr_fault(DisasContext *s)
@@ -1179,64 +1187,182 @@ DISAS_INSN(mulw)
 
 DISAS_INSN(divw)
 {
-    TCGv reg;
-    TCGv tmp;
-    TCGv src;
+    TCGLabel *l1;
+    TCGv t0, src;
+    TCGv quot, rem;
     int sign;
 
     sign = (insn & 0x100) != 0;
-    reg = DREG(insn, 9);
-    if (sign) {
-        tcg_gen_ext16s_i32(QREG_DIV1, reg);
-    } else {
-        tcg_gen_ext16u_i32(QREG_DIV1, reg);
-    }
-    SRC_EA(env, src, OS_WORD, sign, NULL);
-    tcg_gen_mov_i32(QREG_DIV2, src);
+
+    tcg_gen_movi_i32(QREG_CC_C, 0); /* C is always cleared, use as 0 */
+
+    /* dest.l / src.w */
+
+    SRC_EA(env, t0, OS_WORD, sign, NULL);
+
+    src = tcg_temp_local_new_i32();
+    tcg_gen_mov_i32(src, t0);
+    l1 = gen_new_label();
+    tcg_gen_brcondi_i32(TCG_COND_NE, src, 0, l1);
+    tcg_gen_movi_i32(QREG_PC, s->insn_pc);
+    gen_raise_exception(EXCP_DIV0);
+    gen_set_label(l1);
+
+    tcg_gen_movi_i32(QREG_CC_C, 0); /* C is always cleared, use as 0 */
+
+    quot = tcg_temp_new();
+    rem = tcg_temp_new();
     if (sign) {
-        gen_helper_divs(cpu_env, tcg_const_i32(1));
+        tcg_gen_div_i32(quot, DREG(insn, 9), src);
+        tcg_gen_rem_i32(rem, DREG(insn, 9), src);
+        tcg_gen_ext16s_i32(QREG_CC_V, quot);
+        tcg_gen_movi_i32(src, -1);
+        tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_V,
+                            QREG_CC_V, quot,
+                            QREG_CC_C /* 0 */, src /* -1 */);
     } else {
-        gen_helper_divu(cpu_env, tcg_const_i32(1));
+        tcg_gen_divu_i32(quot, DREG(insn, 9), src);
+        tcg_gen_remu_i32(rem, DREG(insn, 9), src);
+        tcg_gen_shri_i32(QREG_CC_V, quot, 16);
+        tcg_gen_movi_i32(src, -1);
+        tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_V,
+                            QREG_CC_V, QREG_CC_C /* 0 */,
+                            QREG_CC_V /* 0 */, src /* -1 */);
     }
+    tcg_temp_free(src);
 
-    tmp = tcg_temp_new();
-    src = tcg_temp_new();
-    tcg_gen_ext16u_i32(tmp, QREG_DIV1);
-    tcg_gen_shli_i32(src, QREG_DIV2, 16);
-    tcg_gen_or_i32(reg, tmp, src);
+    /* result rem:quot */
+
+    tcg_gen_ext16u_i32(quot, quot);
+    tcg_gen_deposit_i32(quot, quot, rem, 16, 16);
+    tcg_temp_free(rem);
+
+    /* on overflow, operands and flags are unaffected */
+
+    tcg_gen_movcond_i32(TCG_COND_EQ, DREG(insn, 9),
+                        QREG_CC_V, QREG_CC_C /* zero */,
+                        quot, DREG(insn, 9));
+    tcg_gen_ext16s_i32(quot, quot);
+    tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_Z,
+                        QREG_CC_V, QREG_CC_C /* zero */,
+                        quot, QREG_CC_Z);
+    tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_N,
+                        QREG_CC_V, QREG_CC_C /* zero */,
+                        quot, QREG_CC_N);
+    tcg_temp_free(quot);
 
     set_cc_op(s, CC_OP_FLAGS);
 }
 
 DISAS_INSN(divl)
 {
-    TCGv num;
-    TCGv den;
-    TCGv reg;
+    TCGLabel *l1;
+    TCGv t0, den, minusone, quot, rem;
+    TCGv_i64 num64, den64, quot64, rem64;
     uint16_t ext;
+    int sign;
 
     ext = read_im16(env, s);
-    if (ext & 0x87f8) {
+
+    if ((ext & 0x400) && !m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
         gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
         return;
     }
-    num = DREG(ext, 12);
-    reg = DREG(ext, 0);
-    tcg_gen_mov_i32(QREG_DIV1, num);
-    SRC_EA(env, den, OS_LONG, 0, NULL);
-    tcg_gen_mov_i32(QREG_DIV2, den);
-    if (ext & 0x0800) {
-        gen_helper_divs(cpu_env, tcg_const_i32(0));
+
+    sign = ext & 0x0800;
+
+    tcg_gen_movi_i32(QREG_CC_C, 0); /* used as 0 later */
+
+    SRC_EA(env, t0, OS_LONG, 0, NULL);
+
+    den = tcg_temp_local_new_i32();
+    tcg_gen_mov_i32(den, t0);
+    l1 = gen_new_label();
+    tcg_gen_brcondi_i32(TCG_COND_NE, den, 0, l1);
+    tcg_gen_movi_i32(QREG_PC, s->insn_pc);
+    gen_raise_exception(EXCP_DIV0);
+    gen_set_label(l1);
+
+    num64 = tcg_temp_new_i64();
+    den64 = tcg_temp_new_i64();
+    quot64 = tcg_temp_new_i64();
+    rem64 = tcg_temp_new_i64();
+    if (ext & 0x400) {
+        tcg_gen_concat_i32_i64(num64, DREG(ext, 12), DREG(ext, 0));
+    } else {
+        if (sign) {
+            tcg_gen_ext_i32_i64(num64, DREG(ext, 12));
+        } else {
+            tcg_gen_extu_i32_i64(num64, DREG(ext, 12));
+        }
+    }
+
+    if (sign) {
+        tcg_gen_ext_i32_i64(den64, den);
+        tcg_gen_div_i64(quot64, num64, den64);
+        tcg_gen_rem_i64(rem64, num64, den64);
+    } else {
+        tcg_gen_extu_i32_i64(den64, den);
+        tcg_gen_divu_i64(quot64, num64, den64);
+        tcg_gen_remu_i64(rem64, num64, den64);
+    }
+    tcg_temp_free_i64(den64);
+    tcg_temp_free_i64(num64);
+
+    /* compute result and overflow flag */
+
+    quot = tcg_temp_new();
+    tcg_gen_extr_i64_i32(quot, QREG_CC_V, quot64);
+
+    rem = tcg_temp_new();
+    minusone = tcg_const_i32(-1);
+    if (sign) {
+        tcg_gen_ext32s_i64(quot64, quot64);
+        tcg_gen_extrh_i64_i32(rem, quot64);
+        tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_V,
+                            QREG_CC_V, rem,
+                            QREG_CC_C /* 0 */, minusone /* -1 */);
     } else {
-        gen_helper_divu(cpu_env, tcg_const_i32(0));
+        tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_V,
+                            QREG_CC_V, QREG_CC_C /* 0 */ ,
+                            QREG_CC_V /* 0 */, minusone /* -1 */);
     }
-    if ((ext & 7) == ((ext >> 12) & 7)) {
-        /* div */
-        tcg_gen_mov_i32 (reg, QREG_DIV1);
+    tcg_temp_free(minusone);
+    tcg_temp_free_i64(quot64);
+
+    tcg_gen_extrl_i64_i32(rem, rem64);
+    tcg_temp_free_i64(rem64);
+
+    /* on overflow, operands and flags are unaffected */
+
+    if (m68k_feature(s->env, M68K_FEATURE_CF_ISA_A)) {
+        if (REG(ext, 0) == REG(ext, 12)) {
+            /* div */
+            tcg_gen_movcond_i32(TCG_COND_EQ, DREG(ext, 12),
+                                QREG_CC_V, QREG_CC_C /* zero */ ,
+                                quot, DREG(ext, 12));
+        } else {
+            /* rem */
+            tcg_gen_movcond_i32(TCG_COND_EQ, DREG(ext, 0),
+                                QREG_CC_V, QREG_CC_C /* zero */ ,
+                                rem, DREG(ext, 0));
+        }
     } else {
-        /* rem */
-        tcg_gen_mov_i32 (reg, QREG_DIV2);
+        tcg_gen_movcond_i32(TCG_COND_EQ, DREG(ext, 0),
+                            QREG_CC_V, QREG_CC_C /* zero */ ,
+                            rem, DREG(ext, 0));
+        tcg_gen_movcond_i32(TCG_COND_EQ, DREG(ext, 12),
+                            QREG_CC_V, QREG_CC_C /* zero */ ,
+                            quot, DREG(ext, 12));
     }
+    tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_Z,
+                        QREG_CC_V, QREG_CC_C /* zero */ ,
+                        quot, QREG_CC_Z);
+    tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_N,
+                        QREG_CC_V, QREG_CC_C /* zero */ ,
+                        quot, QREG_CC_N);
+    tcg_temp_free(quot);
+
     set_cc_op(s, CC_OP_FLAGS);
 }
 
-- 
2.5.5

  parent reply	other threads:[~2016-05-04 21:10 UTC|newest]

Thread overview: 131+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-04 20:11 [Qemu-devel] [PATCH 00/52] 680x0 instructions emulation Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 01/52] target-m68k: fix DEBUG_DISPATCH Laurent Vivier
2016-05-06 16:34   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 02/52] target-m68k: Build the opcode table only once to avoid multithreading issues Laurent Vivier
2016-05-06 16:35   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 03/52] target-m68k: define m680x0 CPUs and features Laurent Vivier
2016-05-06 16:35   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 04/52] target-m68k: manage scaled index Laurent Vivier
2016-05-06 16:36   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 05/52] target-m68k: introduce read_imXX() functions Laurent Vivier
2016-05-06 16:36   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 06/52] target-m68k: set disassembler mode to 680x0 or coldfire Laurent Vivier
2016-05-06 16:37   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 07/52] target-m68k: add bkpt instruction Laurent Vivier
2016-05-06 16:42   ` Richard Henderson
2016-05-07  7:08     ` Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 08/52] target-m68k: define operand sizes Laurent Vivier
2016-05-06 16:43   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 09/52] target-m68k: set PAGE_BITS to 12 for m68k Laurent Vivier
2016-05-06 16:44   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 10/52] target-m68k: REG() macro cleanup Laurent Vivier
2016-05-06 16:44   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 11/52] target-m68k: allow to update flags with operation on words and bytes Laurent Vivier
2016-05-06 16:45   ` Richard Henderson
2016-05-07  7:19     ` Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 12/52] target-m68k: Replace helper_xflag_lt with setcond Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 13/52] target-m68k: update CPU flags management Laurent Vivier
2016-05-06 16:46   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 14/52] target-m68k: update move to/from ccr/sr Laurent Vivier
2016-05-06 16:47   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 15/52] target-m68k: don't update cc_dest in helpers Laurent Vivier
2016-05-06 16:47   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 16/52] target-m68k: update CPU flags management Laurent Vivier
2016-05-06 16:47   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 17/52] target-m68k: Print flags properly Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 18/52] target-m68k: Some fixes to SR and flags management Laurent Vivier
2016-05-06 16:49   ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 19/52] target-m68k: terminate cpu dump with newline Laurent Vivier
2016-05-06 16:49   ` Richard Henderson
2016-05-06 17:41   ` Andreas Schwab
2016-05-04 20:12 ` [Qemu-devel] [PATCH 20/52] target-m68k: Remove incorrect clearing of cc_x Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 21/52] target-m68k: Reorg flags handling Laurent Vivier
2016-05-06 16:51   ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 22/52] target-m68k: Introduce DisasCompare Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 23/52] target-m68k: Use setcond for scc Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 24/52] target-m68k: Optimize some comparisons Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 25/52] target-m68k: Optimize gen_flush_flags Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 26/52] target-m68k: Inline shifts Laurent Vivier
2016-05-06 16:53   ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 27/52] target-m68k: Inline addx, subx, negx Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 28/52] target-m68k: add addx/subx/negx ops Laurent Vivier
2016-05-06 17:11   ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 29/52] target-m68k: factorize flags computing Laurent Vivier
2016-05-06 17:11   ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 30/52] target-m68k: add scc/dbcc Laurent Vivier
2016-05-06 17:18   ` Richard Henderson
2016-05-06 17:44     ` Andreas Schwab
2016-05-04 20:12 ` [Qemu-devel] [PATCH 31/52] target-m68k: some bit ops cleanup Laurent Vivier
2016-05-06 17:20   ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 32/52] target-m68k: bitfield ops Laurent Vivier
2016-05-06 19:11   ` Richard Henderson
2016-05-04 21:08 ` Laurent Vivier [this message]
2016-05-04 21:08   ` [Qemu-devel] [PATCH 34/52] target-m68k: add 64bit mull Laurent Vivier
2016-05-06 19:48     ` Richard Henderson
2016-05-04 21:08   ` [Qemu-devel] [PATCH 35/52] target-m68k: inline rotate ops Laurent Vivier
2016-05-06 20:28     ` Richard Henderson
2016-05-04 21:08   ` [Qemu-devel] [PATCH 36/52] target-m68k: inline shift ops Laurent Vivier
2016-05-06 20:53     ` Richard Henderson
2016-05-04 21:08   ` [Qemu-devel] [PATCH 37/52] target-m68k: add cas/cas2 ops Laurent Vivier
2016-05-06 21:29     ` Richard Henderson
2016-05-04 21:08   ` [Qemu-devel] [PATCH 38/52] target-m68k: add linkl Laurent Vivier
2016-05-06 21:30     ` Richard Henderson
2016-05-04 21:08   ` [Qemu-devel] [PATCH 39/52] target-m68k: movem Laurent Vivier
2016-05-06 21:45     ` Richard Henderson
2016-05-06 19:44   ` [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs Richard Henderson
2016-05-04 21:20 ` [Qemu-devel] [PATCH 40/52] target-m68k: add exg ops Laurent Vivier
2016-05-04 21:20   ` [Qemu-devel] [PATCH 41/52] target-m68k: add addressing modes to not Laurent Vivier
2016-05-06 21:47     ` Richard Henderson
2016-05-04 21:20   ` [Qemu-devel] [PATCH 42/52] target-m68k: eor can manage word and byte operands Laurent Vivier
2016-05-06 21:48     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 43/52] target-m68k: or " Laurent Vivier
2016-05-06 21:49     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 44/52] target-m68k: and " Laurent Vivier
2016-05-06 21:49     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 45/52] target-m68k: suba/adda can manage word operand Laurent Vivier
2016-05-06 21:50     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 46/52] target-m68k: introduce byte and word cc_ops Laurent Vivier
2016-05-06 21:53     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 47/52] target-m68k: add addressing modes to neg Laurent Vivier
2016-05-06 21:54     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 48/52] target-m68k: add/sub manage word and byte operands Laurent Vivier
2016-05-06 21:57     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 49/52] target-m68k: cmp manages word and bytes operands Laurent Vivier
2016-05-06 21:57     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 50/52] target-m68k: immediate ops manage word and byte operands Laurent Vivier
2016-05-06 21:59     ` Richard Henderson
2016-05-04 21:21   ` [Qemu-devel] [PATCH 51/52] target-m68k: add cmpm Laurent Vivier
2016-05-06 22:00     ` Richard Henderson
2016-05-07 19:01       ` Laurent Vivier
2016-05-07 21:50         ` Peter Maydell
2016-05-08  9:07           ` Laurent Vivier
2016-05-08 10:44             ` Peter Maydell
2016-05-04 21:21   ` [Qemu-devel] [PATCH 52/52] target-m68k: sr/ccr cleanup Laurent Vivier
2016-05-06 22:02     ` Richard Henderson
2016-05-06 21:47   ` [Qemu-devel] [PATCH 40/52] target-m68k: add exg ops Richard Henderson
2016-05-06  9:35 ` [Qemu-devel] [PATCH 00/52] 680x0 instructions emulation Andreas Schwab
2016-05-06  9:54   ` Laurent Vivier
2016-05-06 10:15     ` Andreas Schwab
2016-05-06 11:40       ` John Paul Adrian Glaubitz
2016-05-06 12:44         ` Andreas Schwab
2016-05-06 13:02           ` John Paul Adrian Glaubitz
2016-05-06 13:24             ` Andreas Schwab
2016-05-06 13:45               ` John Paul Adrian Glaubitz
2016-05-06 13:48                 ` Andreas Schwab
2016-05-06 13:53                   ` John Paul Adrian Glaubitz
2016-05-06 13:53       ` Laurent Vivier
2016-05-06 13:58         ` Andreas Schwab
2016-05-06 14:25         ` Andreas Schwab
2016-05-06 14:47           ` Andreas Schwab
2016-05-06 11:40     ` John Paul Adrian Glaubitz
2016-05-06 11:45       ` Alexander Graf
2016-05-06 11:57         ` Laurent Vivier
2016-05-06 12:03           ` Peter Maydell
2016-05-12 21:17     ` John Paul Adrian Glaubitz
2016-05-12 21:20       ` Laurent Vivier
     [not found]       ` <D2F89431-FF87-456A-A628-7F8ADCDDAFC7@suse.de>
2016-05-12 21:25         ` John Paul Adrian Glaubitz
     [not found]           ` <C662446E-C86D-4838-83C5-14E8E6C52D2A@suse.de>
2016-05-12 21:32             ` John Paul Adrian Glaubitz
2016-05-12 21:30         ` Laurent Vivier
2016-05-06 10:06 ` Alexander Graf
2016-05-06 10:30   ` [Qemu-devel] [PATCH] MAINTAINERS: update M68K entry Laurent Vivier
2016-05-12  7:55     ` Thomas Huth

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