[PATCH 6/7] drm/i915: Clean up rotation DSPCNTR/DVSCNTR/etc. setup

From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [PATCH 6/7] drm/i915: Clean up rotation DSPCNTR/DVSCNTR/etc. setup
Date: Wed, 20 Jul 2016 16:18:11 +0300	[thread overview]
Message-ID: <1469020693-24356-7-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1469020693-24356-1-git-send-email-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move the plane control register rotation setup away from the
coordinate munging code. This will result in neater looking
code once we add reflection support for CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++--------------
 drivers/gpu/drm/i915/intel_sprite.c  | 28 +++++++++++++++-------------
 2 files changed, 29 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 79c1a8b89d1d..88a7c4173715 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2674,6 +2674,9 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
 	    obj->tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
+	if (rotation & BIT(DRM_ROTATE_180))
+		dspcntr |= DISPPLANE_ROTATE_180;
+
 	if (IS_G4X(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
@@ -2689,8 +2692,6 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
 	}
 
 	if (rotation & BIT(DRM_ROTATE_180)) {
-		dspcntr |= DISPPLANE_ROTATE_180;
-
 		x += (crtc_state->pipe_src_w - 1);
 		y += (crtc_state->pipe_src_h - 1);
 
@@ -2783,6 +2784,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
 	if (obj->tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
+	if (rotation & BIT(DRM_ROTATE_180))
+		dspcntr |= DISPPLANE_ROTATE_180;
+
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
@@ -2792,19 +2796,15 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
 					  fb->pitches[0], rotation);
 	linear_offset -= intel_crtc->dspaddr_offset;
 
-	if (rotation & BIT(DRM_ROTATE_180)) {
-		dspcntr |= DISPPLANE_ROTATE_180;
-
-		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
-			x += (crtc_state->pipe_src_w - 1);
-			y += (crtc_state->pipe_src_h - 1);
+	/* HSW and BDW does this automagically in hardware */
+	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) &&
+	    rotation & BIT(DRM_ROTATE_180)) {
+		x += (crtc_state->pipe_src_w - 1);
+		y += (crtc_state->pipe_src_h - 1);
 
-			/* Finding the last pixel of the last line of the display
-			data and adding to linear_offset*/
-			linear_offset +=
-				(crtc_state->pipe_src_h - 1) * fb->pitches[0] +
-				(crtc_state->pipe_src_w - 1) * cpp;
-		}
+		linear_offset +=
+			(crtc_state->pipe_src_h - 1) * fb->pitches[0] +
+			(crtc_state->pipe_src_w - 1) * cpp;
 	}
 
 	intel_crtc->adjusted_x = x;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 6b815d57d75a..14173f53f520 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -433,6 +433,9 @@ vlv_update_plane(struct drm_plane *dplane,
 	if (obj->tiling_mode != I915_TILING_NONE)
 		sprctl |= SP_TILED;
 
+	if (rotation & BIT(DRM_ROTATE_180))
+		sprctl |= SP_ROTATE_180;
+
 	/* Sizes are 0 based */
 	src_w--;
 	src_h--;
@@ -445,8 +448,6 @@ vlv_update_plane(struct drm_plane *dplane,
 	linear_offset -= sprsurf_offset;
 
 	if (rotation & BIT(DRM_ROTATE_180)) {
-		sprctl |= SP_ROTATE_180;
-
 		x += src_w;
 		y += src_h;
 		linear_offset += src_h * fb->pitches[0] + src_w * cpp;
@@ -555,6 +556,9 @@ ivb_update_plane(struct drm_plane *plane,
 	if (obj->tiling_mode != I915_TILING_NONE)
 		sprctl |= SPRITE_TILED;
 
+	if (rotation & BIT(DRM_ROTATE_180))
+		sprctl |= SPRITE_ROTATE_180;
+
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 	else
@@ -577,15 +581,12 @@ ivb_update_plane(struct drm_plane *plane,
 						   fb->pitches[0], rotation);
 	linear_offset -= sprsurf_offset;
 
-	if (rotation & BIT(DRM_ROTATE_180)) {
-		sprctl |= SPRITE_ROTATE_180;
-
-		/* HSW and BDW does this automagically in hardware */
-		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
-			x += src_w;
-			y += src_h;
-			linear_offset += src_h * fb->pitches[0] + src_w * cpp;
-		}
+	/* HSW and BDW does this automagically in hardware */
+	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) &&
+	    rotation & BIT(DRM_ROTATE_180)) {
+		x += src_w;
+		y += src_h;
+		linear_offset += src_h * fb->pitches[0] + src_w * cpp;
 	}
 
 	if (key->flags) {
@@ -696,6 +697,9 @@ ilk_update_plane(struct drm_plane *plane,
 	if (obj->tiling_mode != I915_TILING_NONE)
 		dvscntr |= DVS_TILED;
 
+	if (rotation & BIT(DRM_ROTATE_180))
+		dvscntr |= DVS_ROTATE_180;
+
 	if (IS_GEN6(dev))
 		dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 
@@ -715,8 +719,6 @@ ilk_update_plane(struct drm_plane *plane,
 	linear_offset -= dvssurf_offset;
 
 	if (rotation & BIT(DRM_ROTATE_180)) {
-		dvscntr |= DVS_ROTATE_180;
-
 		x += src_w;
 		y += src_h;
 		linear_offset += src_h * fb->pitches[0] + src_w * cpp;
-- 
2.7.4

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